TSEV83102G0B - Evaluation Board User Guide
4-1
Rev. 2166B–BDC–04/03
Section 4
Application Information
4.1
Introduction
For this section, also refer to the product "Main features" (TS83102G0B Datasheet).
More particularly, refer to sections related to single-ended and differential input
configurations.
4.2
Analog Inputs
The analog inputs can be entered in differential or single-ended mode without any high
speed performance degradation.
The board digitizes single-ended signals by choosing either input and leaving the other
input open, as the latter is on-board 50
Ω
terminated. The nominal in-phase inputs are
V
IN
(See Section 3).
4.3
Clock Inputs
The clock inputs can be entered in differential or single-ended mode without any perfor-
mance degradation for a clock frequency up to 500 MHz. At higher rates, it is
recommended to drive the clock inputs differentially. Moreover, the typical in phase
clock input amplitude is 1V peak to peak, centered on 0V (Ground), or -1.3V (ECL) on
common mode.
As for the analog input, either clock input can be chosen (if the single-ended output
mode is used), leaving the other input open, as both clock inputs are on-chip 50
Ω
termi-
nated. The nominal in-phase clock input is CLK (Section 3).
4.4
Setting the
Digital Output
Data Format
For this section, refer to the Evaluation Board Electrical schematic and to the compo-
nents placement document (respectively Figure 6-1 on page -2 and Figure 6-6 on page
-3).
Refer also to the TS83102G0B specification about digital output coding.
The TS83102G0B delivers data in natural binary code or in Gray code. If the B/GB input
is left floating or tied to GND the data format selected will be natural binary, if this input
is tied to V
EE
the data will follow the Gray code.
Use the jumper denoted B/GB to select the output data port format:
If B/GB is left floating or tied to GND, the data output format is true binary.
If B/GB is tied to V
EE
or driven with ECL low level, the data outputs are in the Gray
format.
