109
ATmega103(L)
0945G–09/01
As an alternative to using the RESET signal, PEN can be held low during Power-
on Reset while SCK is set to “0”. In this case, only the PEN value at Power-on
Reset is important. If a crystal is not connected across pins XTAL1 and XTAL2,
apply a clock signal to the XTAL1 pin. If the programmer cannot guarantee that
SCK is held low during power-up, the PEN method cannot be used. The device
must be powered down in order to commence normal operation when using this
method.
2.
Wait for at least 20 ms and enable serial programming by sending the Program-
ming Enable serial instruction to pin PE0(PDI/RXD).
3.
The serial programming instructions will not work if the communication is out of
synchronization. When in sync, the second byte ($53) will echo back when issu-
ing the third byte of the Programming Enable instruction. Whether the echo is
correct or not, all four bytes of the instruction must be transmitted. If the $53 did
not echo back, give SCK a positive pulse and issue a new Programming Enable
instruction. If the $53 is not seen within 32 attempts, there is no functional device
connected.
4.
If a chip erase is performed (must be done to erase the Flash), wait at least (2 x
t
WD_FLASH
), give RESET a positive pulse of at least two XTAL1 cycles duration
after SCK has been set to “0”, and start over from step 2.
5.
The Flash is programmed one page at a time. The memory page is loaded one
byte at a time by supplying the 7 LSB of the address and data together with the
Load Program Memory Page instruction. The Program Memory Page is stored
by loading the Write Program Memory Page instruction with the 9 MSB of the
address. The next page can be written after t
WD_FLASH
, i.e., writing 256 bytes
takes t
WD_FLASH
. Accessing the serial programming interface before the Flash
write operation completes can result in incorrect programming.
6.
The EEPROM array is programmed one byte at a time by supplying the address
and data together with the appropriate Write instruction. An EEPROM memory
location is first automatically erased before new data is written. If polling is not
used, the user must wait at least t
WD_EEPROM
before issuing the next byte.
(Please refer to Table 42.)
7.
Any memory location can be verified by using the Read instruction, which returns
the content at the selected address at serial output PE1(PDO/TXD).
8.
At the end of the programming session, RESET can be set high to commence
normal operation.
9.
Power-off sequence (if needed): Set XTAL1 to “0” (if a crystal is not used). Set
RESET to “1”. Turn V
CC
power off.
Table 42 shows the actual delays used in this section.
Please note: The MISO pin is not high-Z during serial programming.
Data Polling for the EEPROM
When a new EEPROM byte has been written and is being programmed into the
EEPROM, reading the address location being programmed will first give the value P1
(please refer to Table 43) until the auto-erase is finished, and then the value P2.
At the time the device is ready for a new EEPROM byte, the programmed value will read
correctly. This is used to determine when the next byte can be written. This will not work
for the values P1 and P2, so when programming these values, the user will have to wait
for at least the prescribed time
t
WD_EEPROM
(please refer to Table 42) before programming
the next byte. As a chip-erased device contains $FF in all locations, programming of
addresses that are meant to contain $FF can be skipped. This does not apply if the
EEPROM is reprogrammed without chip erasing the device.
