AT90S/LS4434 and AT90S/LS8535
24
Interrupt Handling
The AT90S4434/8535 has two 8-bit interrupt mask control registers: GIMSK (General Interrupt Mask register) and TIMSK
(Timer/Counter Interrupt Mask register).
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user soft-
ware can set (one) the I-bit to enable nested interrupts. The I-bit is set (one) when a Return from Interrupt instruction (RETI)
is executed.
When the Program Counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, hard-
ware clears the corresponding flag that generated the interrupt. Some of the interrupt flags can also be cleared by writing a
logical “1” to the flag bit position(s) to be cleared. If an interrupt condition occurs when the corresponding interrupt enable
bit is cleared (zero), the interrupt flag will be set and remembered until the interrupt is enabled or the flag is cleared by
software.
If one or more interrupt conditions occur when the global interrupt enable bit is cleared (zero), the corresponding interrupt
flag(s) will be set and remembered until the global interrupt enable bit is set (one) and will be executed by order of priority.
Note that external level interrupt does not have a flag and will only be remembered for as long as the interrupt condition is
active.
Note that the Status Register is not automatically stored when entering an interrupt routine and restored when returning
from an interrupt routine. This must be handled by software.
General Interrupt Mask Register – GIMSK
•
Bit 7 – INT1: External Interrupt Request 1 Enable
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled.
The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU general Control Register (MCUCR) define whether
the external interrupt is activated on rising or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an
interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is
executed from program memory address $002. See also “External Interrupts.”
•
Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled.
The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) define whether
the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an
interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is
executed from program memory address $001. See also “External Interrupts.”
•
Bits 5.0 – Res: Reserved Bits
These bits are reserved bits in the AT90S4434/8535 and always read as zero.
Table 7.
Reset Source Identification
EXTRF
PORF
Reset Source
0
0
Watchdog Reset
0
1
Power-on Reset
1
0
External Reset
1
1
Power-on Reset
Bit
7
6
5
4
3
2
1
0
$3B ($5B)
INT1
INT0
–
–
–
–
–
–
GIMSK
Read/Write
R/W
R/W
R
R
R
R
R
R
Initial value
0
0
0
0
0
0
0
0
