AT90S/LS4434 and AT90S/LS8535
63
Prescaling
Figure 46.
ADC Prescaler
The successive approximation circuitry requires an input clock frequency between 50 kHz and 200 kHz to achieve maxi-
mum resolution. If a resolution of lower than 10 bits is required, the input clock frequency to the ADC can be higher than
200 kHz to achieve a higher sampling rate. See “ADC Characteristics” on page 69 for more details. The ADC module con-
tains a prescaler, which divides the system clock to an acceptable ADC clock frequency.
The ADPS2..0 bits in ADCSR are used to generate a proper ADC clock input frequency from any CPU frequency above
100 kHz. The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSR. The
prescaler keeps running for as long as the ADEN bit is set and is continuously reset when ADEN is low.
When initiating a conversion by setting the ADSC bit in ADCSR, the conversion starts at the following rising edge of the
ADC clock cycle.
A normal conversion takes 13 ADC clock cycles. In certain situations, the ADC needs more clock cycles for initialization
and to minimize offset errors. Extended conversions take 25 ADC clock cycles and occur as the first conversion after the
ADC is switched on (ADEN in ADCSR is set).
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conversion and 13.5 ADC clock
cycles after the start of an extended conversion. When a conversion is complete, the result is written to the ADC data reg-
isters and ADIF is set. In Single Conversion Mode, ADSC is cleared simultaneously. The software may then set ADSC
again and a new conversion will be initiated on the first rising ADC clock edge. In Free Running Mode, a new conversion
will be started immediately after the conversion completes, while ADSC remains high. Using Free Running Mode and an
ADC clock frequency of 200 kHz gives the lowest conversion time with a maximum resolution, 65 µs, equivalent to
15 kSPS. For a summary of conversion times, see Table 27.
7-BIT ADC PRESCALER
ADC CLOCK SOURCE
CK
ADPS0
ADPS1
ADPS2
CK/128
CK/2
CK/4
CK/8
CK/16
CK/32
CK/64
Reset
ADEN
