AT90S/LS4434 and AT90S/LS8535
8
General-purpose Register File
Figure 6 shows the structure of the 32 general-purpose working registers in the CPU.
Figure 6.
AVR CPU General-purpose Working Registers
All the register operating instructions in the instruction set have direct and single-cycle access to all registers. The only
exception is the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI and ORI between a constant and a
register and the LDI instruction for load immediate constant data. These instructions apply to the second half of the regis-
ters in the register file (R16..R31). The general SBC, SUB, CP, AND and OR and all other operations between two
registers or on a single register apply to the entire register file.
As shown in Figure 6, each register is also assigned a data memory address, mapping them directly into the first 32 loca-
tions of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization
provides great flexibility in access of the registers, as the X, Y and Z registers can be set to index any register in the file.
X-register, Y-register and Z-register
The registers R26..R31 have some added functions to their general-purpose usage. These registers are address pointers
for indirect addressing of the Data Space. The three indirect address registers, X, Y and Z, are defined in Figure 7.
Figure 7.
X-, Y- and Z-registers
In the different addressing modes, these address registers have functions as fixed displacement, automatic increment and
decrement (see the descriptions for the different instructions).
7
0
Addr.
R0 $00
R1
$01
R2
$02
…
R13
$0D
General
R14
$0E
Purpose
R15
$0F
Working
R16
$10
Registers
R17
$11
…
R26
$1A
X-register low byte
R27
$1B
X-register high byte
R28
$1C
Y-register low byte
R29
$1D
Y-register high byte
R30
$1E
Z-register low byte
R31
$1F
Z-register high byte
15
0
X-register
7
0
7
0
R27 ($1B)
R26 ($1A)
15
0
Y-register
7
0
7
0
R29 ($1D)
R28 ($1C)
15
0
Z-register
7
0
7
0
R31 ($1F)
R30 ($1E)
