AT90S/LS4434 and AT90S/LS8535
45
• When entering a Power Save Mode after having written to TCNT2, OCR2 or TCCR2, the user must wait until the written
register has been updated if Timer/Counter2 is used to wake up the device. Otherwise, the MCU will go to sleep before
the changes have had any effect. This is extremely important if the Output Compare2 interrupt is used to wake up the
device; Output Compare is disabled during write to OCR2 or TCNT2. If the write cycle is not finished (i.e., the user goes
to sleep before the OCR2UB bit returns to zero), the device will never get a compare match and the MCU will not
wake up.
• If Timer/Counter2 is used to wake up the device from Power Save Mode, precautions must be taken if the user wants to
re-enter Power Save Mode: The interrupt logic needs one TOSC1 cycle to be reset. If the time between wake up and
re-entering Power Save Mode is less than one TOSC1 cycle, the interrupt will not occur and the device will fail to wake
up. If the user is in doubt whether the time before re-entering Power Save is sufficient, the following algorithm can be
used to ensure that one TOSC1 cycle has elapsed:
1.
Write a value to TCCR2, TCNT2 or OCR2.
2.
Wait until the corresponding Update Busy flag in ASSR returns to zero.
3.
Enter Power Save Mode.
• When the asynchronous operation is selected, the 32 kHz oscillator for Timer/Counter2 is always running, except in
Power-down Mode. After a power-up reset or wake-up from power-down, the user should be aware of the fact that this
oscillator might take as long as one second to stabilize. The user is advised to wait for at least one second before using
Timer/Counter2 after power-up or wake-up from power-down. The content of all Timer/Counter2 registers must be
considered lost after a wake-up from power-down due to the unstable clock signal upon start-up, regardless of whether
the oscillator is in use or a clock signal is applied to the TOSC pin.
• Description of wake-up from Power Save Mode when the timer is clocked asynchronously: When the interrupt condition
is met, the wake-up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at
least one before the processor can read the counter value. The interrupt flags are updated three processor cycles after
the processor clock has started. During these cycles, the processor executes instructions, but the interrupt condition is
not readable and the interrupt routine has not started yet.
• During asynchronous operation, the synchronization of the interrupt flags for the asynchronous timer takes three
processor cycles plus one timer cycle. The timer is therefore advanced by at least 1 before the processor can read the
timer value causing the setting of the interrupt flag. The output compare pin is changed on the timer clock and is not
synchronized to the processor clock.
Watchdog Timer
The Watchdog Timer is clocked from a separate on-chip oscillator. By controlling the Watchdog Timer prescaler, the
Watchdog reset interval can be adjusted as shown in Table 22. See characterization data for typical values at other V
CC
levels. The WDR (Watchdog Reset) instruction resets the Watchdog Timer. Eight different clock cycle periods can be
selected to determine the reset period. If the reset period expires without another Watchdog reset, the AT90S4434/8535
resets and executes from the reset vector. For timing details on the Watchdog reset, refer to page 21.
To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be followed when the Watchdog is
disabled. Refer to the description of the Watchdog Timer Control Register for details.
