AT90S/LS4434 and AT90S/LS8535
9
ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general-purpose working registers. Within a
single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided into
three main categories: arithmetic, logical and bit functions.
In-System Programmable Flash Program Memory
The AT90S4434/8535 contains 4K/8K bytes on-chip, In-System Programmable Flash memory for program storage. Since
all instructions are 16- or 32-bit words, the Flash is organized as 2K/4K x 16. The Flash memory has an endurance of at
least 1000 write/erase cycles. The AT90S4434/8535 Program Counter (PC) is 11/12 bits wide, thus addressing the
2048/4096 program memory addresses.
See page 93 for a detailed description on Flash data downloading.
See page 10 for the different program memory addressing modes.
SRAM Data Memory
Figure 8 shows how the AT90S4434/8535 SRAM memory is organized.
Figure 8.
SRAM Organization
The lower 352/608 data memory locations address the Register file, the I/O memory and the internal data SRAM. The first
96 locations address the Register file + I/O memory, and the next 256/512 locations address the internal data SRAM.
The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with
Pre-decrement and Indirect with Post-increment. In the register file, registers R26 to R31 feature the indirect addressing
pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode features 63 address locations reached from the base address given by the Y- or
Z-registers.
Register File
R0
R1
R2
R29
R30
R31
I/O Registers
$00
$01
$02
...
$3D
$3E
$3F
...
$0000
$0001
$0002
$001D
$001E
$001F
$0020
$0021
$0022
...
$005D
$005E
$005F
...
Data Address Space
$0060
$0061
$015E/$025E
$015F/$025F
...
Internal SRAM
