AT90S/LS4434 and AT90S/LS8535
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Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logical “1” to the flag. When the SREG
I-bit and TOIE0 (Timer/Counter0 Overflow Interrupt Enable) and TOV0 are set (one), the Timer/Counter0 Overflow Inter-
rupt is executed.
External Interrupts
The external interrupts are triggered by the INT1 and INT0 pins. Observe that, if enabled, the interrupts will trigger even if
the INT0/INT1 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external
interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the
MCU Control Register (MCUCR). When the external interrupt is enabled and is configured as level-triggered, the interrupt
will trigger as long as the pin is held low.
The external interrupts are set up as described in the specification for the MCU Control Register (MCUCR).
Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. Four clock cycles after
the interrupt flag has been set, the program vector address for the actual interrupt handling routine is executed. During this
4-clock-cycle period, the Program Counter (2 bytes) is pushed onto the stack and the Stack Pointer is decremented by 2.
The vector is normally a relative jump to the interrupt routine and this jump takes two clock cycles. If an interrupt occurs
during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served.
A return from an interrupt handling routine (same as for a subroutine call routine) takes four clock cycles. During these four
clock cycles, the Program Counter (2 bytes) is popped back from the stack, the Stack Pointer is incremented by 2 and the
I-flag in SREG is set. When the AVR exits from an interrupt, it will always return to the main program and execute one more
instruction before any pending interrupt is served.
MCU Control Register – MCUCR
The MCU Control Register contains control bits for general MCU functions.
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Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the AT90S4434/8535 and always reads zero.
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Bit 6 – SE: Sleep Enable
The SE bit must be set (one) to make the MCU enter the Sleep Mode when the SLEEP instruction is executed. To avoid
the MCU entering the Sleep Mode unless it is the programmer’s purpose, it is recommended to set the Sleep Enable (SE)
bit just before the execution of the SLEEP instruction.
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Bits 5, 4 – SM1/SM0: Sleep Mode Select Bits 1 and 0
These bits select between the three available sleep modes as shown in Table 8.
Bit
7
6
5
4
3
2
1
0
$35 ($55)
–
SE
SM1
SM0
ISC11
ISC10
ISC01
ISC00
MCUCR
Read/Write
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
Table 8.
Sleep Mode Select
SM1
SM0
Sleep Mode
0
0
Idle
0
1
Reserved
1
0
Power-down
1
1
Power Save
