Atmel AT91CAP9, User Manual

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AT91CAP9A-DK Development Kit User Guide 7-5
6321B–CAP–02-Jul-07
For technical details, please refer to the appended schematics: Section 16, sheet 5 (look for regulator
U6) and sheet 14 (look for regulator U10)
7.6 Host USB Port
The mini-AB connector J16 is connected directly to the AT91CAP9 chip. Please refer to the appended
schematics:
Section 16, sheet 7 for in-depth details of its implementation.
7.7 FPGA Connections
7.7.1 FPGA Banking Allocations
As shown in the synoptic in Figure 7-1 “AT91CAP9A-DKZ Mezzanine Block Diagram (see the complete
schematic in Section 16)”, the Altera component has eight different IO banks. Each of these can be pow-
ered separately, thereby allowing different signaling standards of a system to be implemented in parallel.
Banking Allocations:
„ Banks 1, 2 and 3 = user IO going down to motherboard for user extension (PCI64, “Mistral”
connection, USB device interfaces)
„ Banks 4, 5 and 6 (partly) = PISMO-II extension connector
„ Bank 6 (partly) = leftovers allocated between the user I/O grid and EBI/FPGA connector
„ Bank 7 = EBI/FPGA connector
„ Bank 8 = AT91CAP9 connection via MPIO bus.
7.7.2 CAP/MPIO Bus Connections
Table 7-1. MPIO-FPGA Signal Assignment
CAP/MPIO Signal FPGA Pin Alternate Pin Function FPGA Bank
MPIOA00 AG25 8
MPIOA01 AB21 8
MPIOA02 AE22 8
MPIOA03 AF22 8
MPIOA04 AD22 8
MPIOA05 AH28 DQ17B 8
MPIOA06 AK29 DQSn17B 8
MPIOA07 AJ28 DQ17B 8
MPIOA08 AM29 DQ17B 8
MPIOA09 AL29 DQ17B 8
MPIOA10 AK28 DQS17B 8
MPIOA11 AC21 8
MPIOA12 AG21 8
MPIOA13 AK27 DQ16B 8