Atmel AT91CAP9 User Manual Download

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AT91CAP9A-DK Development Kit User Guide

7-59

6321B–CAP–02-Jul-07

DQ15T

E26

FPGA250

F21

FPGA251

DQS16T

B27

FPGA252

DQ16T

A27

FPGA253

DQ16T

A28

FPGA254

DQ16T

D27

FPGA255

DQSn16T

B28

FPGA256

DQ16T

C27

FPGA257

H22

FPGA258

J22

FPGA259

DIFFIO_TX23p

W27

FPGA26

DQS17T

C28

FPGA260

DQ17T

B29

FPGA261

DQ17T

A29

FPGA262

DQ17T

D28

FPGA263

DQSn17T

C29

FPGA264

DQ17T

E28

FPGA265

K22

FPGA266

F25

FPGA267

G22

FPGA268

DATA2

G23

FPGA269

DIFFIO_TX23n

W26

FPGA27

DATA3

H23

FPGA270

DATA4

J23

FPGA271

DATA5

L22

FPGA272

DATA6

F24

FPGA273

DATA7

G24

FPGA274

RDYnBSY

H24

FPGA275

DIFFIO_RX22p

Y29

FPGA28

DIFFIO_RX22n

Y28

FPGA29

CLK3n

INPUT

U29

FPGA3

DIFFIO_TX22p

W25

FPGA30

DIFFIO_TX22n

W24

FPGA31

DIFFIO_RX21p

AB30

FPGA32

DIFFIO_RX21n

AB29

FPGA33

DIFFIO_TX21p

Y27

FPGA34

Table 7-6. FPGA Pins Sorted by Signal Name (Continued)

Bank

Pin Type Name

Other Pin Information

Configuration
Function

Ball

Board Net

Summary of Contents for AT91CAP9

Page 1: ...6321B CAP 02 Jul 07 AT91CAP9A DK Development Kit User Guide ...

Page 2: ...1 2 AT91CAP9A DK Development Kit User Guide 6321B CAP 02 Jul 07 ...

Page 3: ...n 3 AT91CAP DKM Motherboard 3 1 3 1 Block Diagram 3 2 3 2 Clock Circuity 3 3 3 3 Reset Circuity 3 3 3 4 Shutdown Controller 3 3 3 5 Power Supply Circuity 3 3 3 6 Memory 3 3 3 7 Remote Communication 3 3 3 7 1 CAN Interface 3 3 3 7 2 Host USB Interface 3 3 3 7 3 Device USB Interface 3 4 3 7 4 Ethernet Interface 3 4 3 8 Audio Stereo Interface 3 4 3 8 1 AC97 3 4 3 8 2 I2S 3 4 3 9 Analog Interface 3 4 ...

Page 4: ...ion 6 Setting Up the AT91CAP9A DKZ Mezzanine 6 1 6 1 Electrostatic Warning 6 1 6 2 Requirements 6 1 6 3 Layout 6 1 6 3 1 AT91CAP9 Specific 6 1 6 3 2 FPGA Specific Altera Stratix II EP2S90F1020C5 6 2 6 4 Powering Up the Board 6 2 Section 7 AT91CAP9A DKZ Mezzanine Board 7 1 7 1 Block Diagram 7 2 7 2 Reset Path 7 4 7 3 Clocking Paths 7 4 7 3 1 AT91CAP9 Clock Sources 7 4 7 3 2 FPGA Clock Sources 7 4 7...

Page 5: ... 1 10 1 Electrostatic Warning 10 1 10 2 Requirements 10 1 10 3 Layout 10 1 10 4 Powering Up the Board 10 2 Section 11 AT91CAP MEM18 Configuration 11 1 11 1 Configuration 11 1 Section 12 Overview AT91CAP MEM33 CAP 3 3V Memory Board 12 1 12 1 Scope 12 1 12 2 Purpose 12 1 Section 13 Setting Up the AT91CAP MEM33 Board 13 1 13 1 Electrostatic Warning 13 1 13 2 Requirements 13 1 13 3 Layout 13 1 13 4 Po...

Page 6: ... Section 16 AT91CAP9A DKZ Schematics 16 1 16 1 Schematics 16 1 Section 17 AT91CAP MEM18 Schematics 17 1 17 1 Schematics 17 1 Section 18 AT91CAP MEM33 Schematics 18 1 18 1 Schematics 18 1 Section 19 Errata 19 1 19 1 Known Errata 19 1 Section 20 Revision History 20 1 20 1 Revision History 20 1 ...

Page 7: ...ntroller standard product tightly coupled to a high density FPGA that emulates the MP Block The boards also include a range of memories and physical interfaces connectors representing external system components This configuration enables parallel hardware software testing of the application under development at close to operational speed with no penalty for hardware modifications This enables soft...

Page 8: ...pment Kit AT91CAP DKM Motherboard 1 2 Purpose The AT91CAP DKM Motherboard provides all the service items of an AT91CAP9A DK development system That is Power supply input conversion and distribution Standard user interfaces Prototyping interface and extension means Memory extension CAP Mezzanine Motherboard ...

Page 9: ...ATX standard power supply unit AT91CAP9A DKZ mezzanine board see Sections 5 through 8 with a memory extension see sections 9 through 14 2 3 Layout The AT91CAP DKM motherboard features the following on board interfaces ATX power supply connector 2x Full speed Host USB interfaces 100 base TX Ethernet PHY with three status LEDs DBGU serial communication port 4x analog inputs AC97 interface with three...

Page 10: ...otherboard via a stan dard ATX PC power supply The power control signal is connected to the SHDN signal generated by the AT91CAP9 chip from the AT91CAP9A DKZ mezzanine board In case the AT91CAP DKM motherboard has to be powered without a mezzanine or an AT91CAP9 chip in place the Force Power ON jumper J5 must be installed Dual Host USB interface Ethernet interface DBGU port 4x analog inputs CAP me...

Page 11: ...AT91CAP9A DK Development Kit User Guide 3 1 6321B CAP 02 Jul 07 Section 3 AT91CAP DKM Motherboard ...

Page 12: ...D2 GND 3V3 page 6 ISI_D 0 11 ISI_MCK ISI_VSYNC ISI_HSYNC ISI_PCK PA14 PA15 VDDIOP1 TWD TWCK PC20 PC21 MCI1_DA0 MCI1_DA1 MCI1_DA2 MCI1_DA3 MCI1_CDA MCI1_CK MCI0_CDA MCI0_CK MCI0_DA0 MCI0_DA1 MCI0_DA2 MCI0_DA3 MCI MCI ISI PA0 PA3 PA4 PA5 PA1 PA2 SERIAL DEVICES ISI_D 0 11 CTRL1 SCL CTRL2 SDA ISI_VSYNC ISI_HSYNC ISI_MCK ISI_PCK MCI0_DA3 MCI0_DA0 MCI0_DA1 MCI0_DA2 MCI0_CDA MCI0_CD MCI1_CD MCI1_DA3 MCI1...

Page 13: ...passed with jumper J5 3 5 Power Supply Circuity The AT91CAP DKM motherboard derives the necessary system voltages from the ATX supply On board switching regulators provide the following voltage sources 1 2V 1 8V 2 5V 3 6 Memory The only memory resource available on the AT91CAP DKM motherboard is an Atmel serial EEPROM TWI bus connection System memory resources are to be connected directly to the A...

Page 14: ... input This interface has some configuration elements Please refer to Section 4 AT91CAP DKM Configura tion and or AT91CAP DKM Schematics for in depth details 3 8 2 I2S One I2S audio codec MN14 UDA1342TS with the following connectors line out line in 3 9 Analog Interface Four analog inputs range up to 3 3V These are available through the J33 connector and are buffered by a quadruple gain 1 amplifie...

Page 15: ...eripheral extension connectors J17 to J20 This allows the developer to add external hardware components or boards Note Most of the PIO lines already have an assignment on board Therefore be aware of the schematic routing prior to customizing these lines in any way Do not cause electrical con tention as this may potentially damage the boards and the AT91CAP9 chip 3 14 FPGA Extension 3 14 1 Overview...

Page 16: ...3 1 FPGA IO Overlapping Table Net Name Range J8 J10 J9 USB FPGA000 FPGA001 FPGA004 FPGA 093 FPGA098 FPGA117 X FPGA250 FPGA 252 FPGA260 FPGA 262 X X FPGA118 FPGA174 X FPGA175 FPGA 189 FPGA191 FPGA 228 FPGA270 X X FPGA229 FPGA245 X FPGA190 FPGA246 FPGA 249 FPGA253 FPGA 259 FPGA263 FPGA 269 FPGA271 FPGA 275 X X FPGA002 FPGA003 FPGA094 FPGA 097 X 1 J10 6 5 10 196 J8 and J10 as seen on AT91CAP9 DKM fro...

Page 17: ...11 B1 IO DIFFIO_TX28p U23 FPGA6 12 GND 13 B1 IO DIFFIO_TX28n U22 FPGA7 14 GND 15 B1 IO DIFFIO_RX27p W32 FPGA8 16 B1 IO DIFFIO_RX27n W31 FPGA9 17 GND 18 B1 IO DIFFIO_TX27p U28 FPGA10 19 GND 20 B1 IO DIFFIO_TX27n U27 FPGA11 21 B1 IO DIFFIO_RX26p AA32 FPGA12 22 GND 23 B1 IO DIFFIO_RX26n AA31 FPGA13 24 GND 25 B1 IO DIFFIO_TX26p V29 FPGA14 26 B1 IO DIFFIO_TX26n V28 FPGA15 27 GND 28 B1 IO DIFFIO_RX25p Y...

Page 18: ...A30 52 GND 53 B1 IO DIFFIO_TX22n W24 FPGA31 54 GND 55 B1 IO DIFFIO_RX21p AB30 FPGA32 56 B1 IO DIFFIO_RX21n AB29 FPGA33 57 GND 58 B1 IO DIFFIO_TX21p Y27 FPGA34 59 GND 60 B1 IO DIFFIO_TX21n Y26 FPGA35 61 B1 IO DIFFIO_RX20p AC32 FPGA36 62 GND 63 B1 IO DIFFIO_RX20n AC31 FPGA37 64 GND 65 B1 IO DIFFIO_TX20p AA27 FPGA38 66 B1 IO DIFFIO_TX20n AA26 FPGA39 67 GND 68 B1 IO DIFFIO_RX19p AB28 FPGA40 69 GND 70 ...

Page 19: ...88 B1 IO DIFFIO_RX16p AF32 FPGA52 89 GND 90 B1 IO DIFFIO_RX16n AF31 FPGA53 91 B1 IO DIFFIO_TX16p AC27 FPGA54 92 GND 93 B1 IO DIFFIO_TX16n AC26 FPGA55 94 GND 95 B1 IO DIFFIO_RX15p AG32 FPGA56 96 NRST 97 GND 98 B1 IO DIFFIO_RX15n AG31 FPGA57 99 GND 100 B1 IO DIFFIO_TX15p Y23 FPGA58 101 B1 IO DIFFIO_TX15n Y22 FPGA59 102 GND 103 B1 IO DIFFIO_RX14p AC30 FPGA60 104 GND 105 B1 IO DIFFIO_RX14n AC29 FPGA61...

Page 20: ...PGA72 124 GND 125 B1 IO DIFFIO_RX11n AE29 FPGA73 126 B1 IO DIFFIO_TX11p AB24 FPGA74 127 GND 128 B1 IO DIFFIO_TX11n AB23 FPGA75 129 GND 130 B1 IO DIFFIO_RX10p AJ32 FPGA76 131 B1 IO DIFFIO_RX10n AJ31 FPGA77 132 GND 133 B1 IO DIFFIO_TX10p AC25 FPGA78 134 GND 135 B1 IO DIFFIO_TX10n AC24 FPGA79 136 B1 IO DIFFIO_RX9p AF30 FPGA80 137 GND 138 B1 IO DIFFIO_RX9n AF29 FPGA81 139 GND 140 B1 IO DIFFIO_TX9p AD2...

Page 21: ...60 B3 IO DQS16T B27 FPGA252 161 B3 IO DQS17T C28 FPGA260 162 GND 163 B3 IO DQ17T B29 FPGA261 164 GND 165 B3 IO DQ17T A29 FPGA262 166 B2 IO DIFFIO_TX51p K25 FPGA98 167 GND 168 B2 IO DIFFIO_TX51n K24 FPGA99 169 GND 170 B2 IO DIFFIO_RX50p G28 FPGA100 171 B2 IO DIFFIO_RX50n G27 FPGA101 172 GND 173 B2 IO DIFFIO_TX50p H28 FPGA102 174 GND 175 B2 IO DIFFIO_TX50n H27 FPGA103 176 B2 IO DIFFIO_RX49p E30 FPGA...

Page 22: ...ND 195 B2 IO DIFFIO_TX47n L27 FPGA115 196 B2 IO DIFFIO_RX46p G30 FPGA116 197 GND 198 B2 IO DIFFIO_RX46n G29 FPGA117 199 GND Table 3 3 J10 female Pin Assignment Table J10 Pin FPGA Bank FPGA Pin Function Other FPGA Pin Information FPGA Ball Board Net 1 B2 IO DIFFIO_TX46p L26 FPGA118 2 GND 3 B2 IO DIFFIO_TX46n L25 FPGA119 4 GND 5 B2 IO DIFFIO_RX45p H30 FPGA120 6 B2 IO DIFFIO_RX45n H29 FPGA121 7 GND 8...

Page 23: ...DIFFIO_TX42p M27 FPGA134 29 GND 30 B2 IO DIFFIO_TX42n M26 FPGA135 31 B2 IO DIFFIO_RX41p G32 FPGA136 32 GND 33 B2 IO DIFFIO_RX41n G31 FPGA137 34 GND 35 B2 IO DIFFIO_TX41p N25 FPGA138 36 B2 IO DIFFIO_TX41n N24 FPGA139 37 GND 38 B2 IO DIFFIO_RX40p H32 FPGA140 39 GND 40 B2 IO DIFFIO_RX40n H31 FPGA141 41 B2 IO DIFFIO_TX40p N23 FPGA142 42 GND 43 B2 IO DIFFIO_TX40n N22 FPGA143 44 GND 45 B2 IO DIFFIO_RX39...

Page 24: ...A155 64 GND 65 B2 IO DIFFIO_RX36p L30 FPGA156 66 B2 IO DIFFIO_RX36n L29 FPGA157 67 GND 68 B2 IO DIFFIO_TX36p P27 FPGA158 69 GND 70 B2 IO DIFFIO_TX36n P26 FPGA159 71 B2 IO DIFFIO_RX35p N29 FPGA160 72 GND 73 B2 IO DIFFIO_RX35n N28 FPGA161 74 GND 75 B2 IO DIFFIO_TX35p P25 FPGA162 76 B2 IO DIFFIO_TX35n P24 FPGA163 77 GND 78 B2 IO DIFFIO_RX34p M30 FPGA164 79 GND 80 B2 IO DIFFIO_RX34n M29 FPGA165 81 B2 ...

Page 25: ...PGA177 101 B2 IO DIFFIO_TX31p R29 FPGA178 102 GND 103 B2 IO DIFFIO_TX31n R28 FPGA179 104 GND 105 B2 IO DIFFIO_RX30p P32 FPGA180 106 B2 IO DIFFIO_RX30n P31 FPGA181 107 GND 108 B2 IO DIFFIO_TX30p T28 FPGA182 109 GND 110 B2 IO DIFFIO_TX30n T27 FPGA183 111 B2 IO DIFFIO_RX29p R31 FPGA184 112 GND 113 B2 IO DIFFIO_RX29n R30 FPGA185 114 GND 115 B2 IO DIFFIO_TX29p T23 FPGA186 116 B2 IO DIFFIO_TX29n T22 FPG...

Page 26: ...IO F19 FPGA198 136 B3 IO E17 FPGA199 137 GND 138 B3 IO G20 FPGA200 139 GND 140 B3 IO F20 FPGA201 141 B3 IO DQS10T D19 FPGA202 142 GND 143 B3 IO DQ10T B20 FPGA203 144 GND 145 B3 IO DQ10T E19 FPGA204 146 B3 IO DQ10T C20 FPGA205 147 GND 148 B3 IO DQSn10T D20 FPGA206 149 GND 150 B3 IO DQ10T E20 FPGA207 151 B3 IO L19 FPGA208 152 GND 153 B3 IO L18 FPGA209 154 GND 155 B3 IO J19 FPGA210 156 B3 IO K19 FPGA...

Page 27: ... 170 B3 IO H20 FPGA219 171 B3 IO K20 FPGA220 172 GND 173 B3 IO DQS12T D22 FPGA221 174 GND 175 B3 IO DQ12T D23 FPGA222 176 B3 IO DQ12T D21 FPGA223 177 GND 178 B3 IO DQ12T F22 FPGA224 179 GND 180 B3 IO DQSn12T E22 FPGA225 181 B3 IO DQ12T F23 FPGA226 182 GND 183 B3 IO L21 FPGA227 184 GND 185 B3 IO J20 FPGA228 187 GND 189 GND 191 VCCIO1 192 GND 193 VCCIO2 194 GND 195 VCCIO3 Table 3 3 J10 female Pin As...

Page 28: ...in Function Other FPGA Pin Information FPGA Ball Board Net Table 3 4 PCI64 Extension Connector Table J9 Pin FPGA Bank FPGA Pin Function Other FPGA Pin Information FPGA Ball Board Net 1 B2 IO DIFFIO_TX31n R28 FPGA179 2 12VPCI 3 12VPCI 4 B2 IO DIFFIO_RX31p M32 FPGA176 5 B2 IO DIFFIO_RX31n M31 FPGA177 6 GND 7 B2 IO DIFFIO_TX31p R29 FPGA178 8 B2 CLK1p INPUT T30 FPGA175 9 5VPCI 10 5VPCI 11 B2 IO DIFFIO...

Page 29: ... 34 VCCIO2 35 B2 IO CLK0p DIFFIO_RX_C0p T32 FPGA189 36 B2 IO CLK0n DIFFIO_RX_C0n T31 FPGA188 37 VCCIO2 38 B2 IO DIFFIO_TX32n R24 FPGA191 39 B3 IO CLK14p A17 FPGA192 40 GND 41 B3 IO CLK14n B17 FPGA193 42 B3 IO CLK15p C17 FPGA194 43 GND 44 B3 IO CLK15n D17 FPGA195 45 B3 IO K18 FPGA196 46 VCCIO3 47 B3 IO F18 FPGA197 48 B3 IO F19 FPGA198 49 VCCIO3 50 B3 IO E17 FPGA199 51 B3 IO G20 FPGA200 52 GND 53 B3...

Page 30: ...71 B3 IO DQS11T B21 FPGA212 72 GND 73 VCCIO3 74 B3 IO DQ11T A21 FPGA213 75 B3 IO DQ11T C21 FPGA214 76 B3 IO DQ11T A22 FPGA215 77 B3 IO DQSn11T B22 FPGA216 78 VCCIO3 79 GND 80 B3 IO DQ11T C22 FPGA217 81 B3 IO L20 FPGA218 82 VCCIO3 83 B3 IO H20 FPGA219 84 B3 IO K20 FPGA220 85 VCCIO3 86 B3 IO DQS12T D22 FPGA221 87 B3 IO DQ12T D23 FPGA222 88 GND 89 B3 IO DQ12T D21 FPGA223 90 B3 IO DQ12T F22 FPGA224 91...

Page 31: ...3T C24 FPGA232 107 GND 108 B3 IO DQSn13T B24 FPGA233 109 B3 IO DQ13T A24 FPGA234 110 GND 111 B3 IO K21 FPGA235 112 B3 IO H21 FPGA236 113 VCCIO3 114 VCCIO3 115 B3 IO J21 FPGA237 116 B3 IO DQS14T B25 FPGA238 117 5VPCI 118 5VPCI 119 5VPCI 120 5VPCI 121 GND 123 B3 IO DQ14T A25 FPGA239 124 GND 125 B3 IO DQ14T A26 FPGA240 126 B3 IO DQ14T D26 FPGA241 127 VCCIO3 128 B3 IO DQSn14T B26 FPGA242 Table 3 4 PCI...

Page 32: ...2 144 B3 IO DQ16T A27 FPGA253 145 VCCIO3 146 B3 IO DQ16T A28 FPGA254 147 B3 IO DQ16T D27 FPGA255 148 GND 149 B3 IO DQSn16T B28 FPGA256 150 B3 IO DQ16T C27 FPGA257 151 GND 152 B3 IO H22 FPGA258 153 B3 IO J22 FPGA259 154 VCCIO3 155 B3 IO DQS17T C28 FPGA260 156 B3 IO DQ17T B29 FPGA261 157 GND 158 B3 IO DQ17T A29 FPGA262 159 B3 IO DQ17T D28 FPGA263 160 GND 161 B3 IO DQSn17T C29 FPGA264 162 B3 IO DQ17T...

Page 33: ...e 165 B3 IO F25 FPGA267 166 GND 167 B3 IO G22 FPGA268 168 B3 IO G23 FPGA269 169 GND 170 B3 IO H23 FPGA270 171 B3 IO J23 FPGA271 172 VCCIO3 173 B3 IO L22 FPGA272 174 B3 IO F24 FPGA273 175 GND 176 B3 IO G24 FPGA274 177 B3 IO H24 FPGA275 178 GND 181 GND 184 GND Table 3 4 PCI64 Extension Connector Table Continued J9 Pin FPGA Bank FPGA Pin Function Other FPGA Pin Information FPGA Ball Board Net Table 3...

Page 34: ...MN6 2 RCV B3 J23 FPGA271 MN6 4 VM B3 L22 FPGA272 MN6 3 VP B3 F24 FPGA273 MN6 12 VMO FSEO B3 G24 FPGA274 MN6 11 VPO VO B3 H24 FPGA275 MN6 16 SOFTCON Table 3 5 USB Interface and FPGA Connection Continued FPGA Bank FPGA Ball Board Signal Board Component Pin Function Table 3 6 PIO Controller A I O Line Peripheral A Peripheral B Peripheral Usage Powered by PA0 MCI0_DA0 SPI0_MISO SD MMC DATAFLASH SOCKET...

Page 35: ...J27 MCI1_DA1 ISI_D3 VDDIOP1 PA20 MCI1_DA2 ISI_D4 SD MMC SOCKET J29 ISI J27 MCI1_DA2 ISI_D4 VDDIOP1 PA21 MCI1_DA3 ISI_D5 SD MMC SOCKET J29 ISI J27 MCI1_DA3 ISI_D5 VDDIOP1 PA22 TXD0 ISI_D6 ISI J27 ISI_D6 VDDIOP1 PA23 RXD0 ISI_D7 ISI J27 ISI_D7 VDDIOP1 PA24 RTS0 ISI_PCK ISI J27 ISI_PCK VDDIOP1 PA25 CTS0 ISI_HSYNC ISI J27 ISI_HSYNC VDDIOP1 PA26 SCK0 ISI_VSYNC ISI J27 ISI_VSYNC VDDIOP1 PA27 PCK1 ISI_MC...

Page 36: ...PCK AD1 ANALOG INPUT INTERFACE J33 2 AD1 3 VDDIOP0 PB15 SPI1_NPCS0 AD2 ANALOG INPUT INTERFACE J33 2 AD2 3 VDDIOP0 PB16 SPI1_NPCS1 AD3 ANALOG INPUT INTERFACE J33 2 AD3 3 VDDIOP0 PB17 SPI1_NPCS2 AD4 AD4 3 VDDIOP0 PB18 SPI1_NPCS3 AD5 AD5 3 VDDIOP0 PB19 PWM0 AD6 AD6 3 VDDIOP0 PB20 PWM1 AD7 AD7 3 VDDIOP0 PB21 ETXCK TIOA2 ETHERNET RMII INTERFACE MN7 ETXCK VDDIOP0 PB22 ERXDV TIOB2 ETHERNET RMII INTERFACE...

Page 37: ...C13 LCDD9 LCDD14 VDDIOP0 PC14 LCDD10 LCDD15 LCD PANEL CONNECTOR J37 LCDD10 VDDIOP0 PC15 LCDD11 LCDD19 LCD PANEL CONNECTOR J37 LCDD11 VDDIOP0 PC16 LCDD12 LCDD20 LCD PANEL CONNECTOR J37 LCDD12 VDDIOP0 PC17 LCDD13 LCDD21 LCD PANEL CONNECTOR J37 LCDD13 VDDIOP0 PC18 LCDD14 LCDD22 LCD PANEL CONNECTOR J37 LCDD14 VDDIOP0 PC19 LCDD15 LCDD23 LCD PANEL CONNECTOR J37 LCDD15 VDDIOP0 PC20 LCDD16 ETX2 SD MMC DAT...

Page 38: ...YPADS PD8 as KBD2 row 2 VDDIOM PD9 EBI_CFCE1 SCK2 4X4 KEYPADS PD9 as KBD3 row 3 VDDIOM PD10 EBI_CFCE2 SCK1 4X4 KEYPADS PD10 as KBD4 column 0 VDDIOM PD11 EBI_NCS2 4X4 KEYPADS PD11 as KBD5 column 1 VDDIOM PD12 EBI_A23 4X4 KEYPADS PD12 as KBD6 column 2 VDDIOM PD13 EBI_A24 4X4 KEYPADS PD13 as KBD7 column 3 VDDIOM PD14 EBI_A25_CF RNW VDDIOM PD15 EBI_NCS3 N ANDCS VDDIOM PD16 EBI_D16 VDDIOM PD17 EBI_D17 ...

Page 39: ...ional PCI voltages enabling J11 13 15 FPGA USB interfaces speed selection R36 37 MN6 USB PHYs mode selection R27 28 MN5 R18 19 MN4 J22 Ethernet PHY auto MDIX control J25 apply CAN termination C45 48 USB lines filtering R93 94 95 VDDIOP1 voltage selection R104 107 AC97 clocking selection R123 125 MIC input biasing selection R171 connects 3 3V to ADC inputs connector R153 154 use alternate input cha...

Page 40: ...pply power on To be installed in case the SHDN signal normally provided by the AT91CAP9 chip is non operating or absent for some reason R104 107 ON ON use 1K Ohm resistors Select the AC97 AD1981B clock frequency Refer to AT91CAP DKM Schematics and or the AD1981B datasheet for in depth explanations R123 125 OFF OFF Optional MIC input biasing to VREFOUT for the AC97 AD1981B chip Refer to AT91CAP DKM...

Page 41: ...7 ON OFF Selects ISP1105BS PHY MN6 mode input Please refer to the datasheet of this device for in depth details R9 10 11 OFF OFF OFF Enable additional service voltages to be routed to the PCI64 connector J9 Solder 0 Ohm resistors to do so R93 94 95 ON OFF OFF Select CAP VDDIOP1 voltage On AT91CAP9 chip VDDIOP1 is part of the PIOA port and is dedicated to the ISI interface Connector J27 By default ...

Page 42: ...4 4 AT91CAP9A DK Development Kit User Guide 6321B CAP 02 Jul 07 ...

Page 43: ...9 processor applications Section 5 through Section 8 provide essential usage documentation for the AT91CAP9 Altera mezzanine board AT91CAP9A DKZ Figure 5 1 AT91CAP9A DKZ Overview 5 2 Purpose The AT91CAP9A DKZ mezzanine provides a configurable processor AT91CAP9 and its associated FPGA both being at the heart of an AT91CAP9A DK development system layout Memory extension AT91CAP9A DKZ Mezzanine Moth...

Page 44: ...5 2 AT91CAP9A DK Development Kit User Guide 6321B CAP 02 Jul 07 ...

Page 45: ...pment system the following items are needed AT91CAP9A DKZ mezzanine Memory extension board see sections 9 through 14 AT91CAP DKM motherboard see sections 1 through 4 PC ATX standard power supply unit 6 3 Layout The board features essentially an AT91CAP9 chip connected to an FPGA to be used for prototyping the configurable part of the AT91CAP9 chip Around these two major components of the AT91CAP9A...

Page 46: ...91CAP9A DK system is powered through the AT91CAP DKM motherboard via a stan dard ATX PC power supply The power control signal is connected to the SHDN signal generated by the AT91CAP9 chip from the AT91CAP9A DKZ mezzanine board High Speed Host USB port FPGA configuration memory port Byte Blaster FPGA configuration memory FPGA extension PISMO II format FPGA clock sources oscillator and SMB FPGA ext...

Page 47: ...AT91CAP9A DK Development Kit User Guide 7 1 6321B CAP 02 Jul 07 Section 7 AT91CAP9A DKZ Mezzanine Board ...

Page 48: ... PISMO_DM_DQSA_DH PISMO_DM_DQSA_DL PISMO_DM_DQSB_DL PISMO_DM_DQSB_DH PISMO_DM_DQSC_DL PISMO_DM_DQSC_DH PISMO_DM_DQSD_DL PISMO_DM_DQSD_DH PISMO_FS 0 9 PISMO_DM 0 36 PISMO_DM_DA 0 7 PISMO_DM_DB 0 7 PISMO_DM_DC 0 7 PISMO_DM_DD 0 7 SODIMM_C 0 53 SODIMM_D 0 31 SODIMM_DQS 0 1 MPIOA 0 31 NRST MPIOB 0 44 VCCIO_8 VCCPD VCCINT VCCIO_4 VCCIO_6 VCCIO_7 GND 3V3 2V5 1V8 VCCIO_1 VCCIO_2 VCCIO_3 VCCIO_5 S2_TDO S2...

Page 49: ...AF 40 05 0 SM 8 2 A K SAMTEC SEAF 40 05 0 SM 8 2 A K CAP9 PIO bus 128 FPGA EBI bus 89 USER IO GRID bus 72 PISMO II bus 214 USER IO bus 276 CAP9 EBI bus 85 CAP9 MPIO bus 77 JTAG header except TDO J3 J4 J5 SODIMM 144 EBI bus for external memory board connection SODIMM 144 EBI bus for external memory board connection PISMO II extension connector PIO A EBI PIO B S Y S PIO C P I O D USB MPIO PIO D ANAL...

Page 50: ...ser clock connector SMB format connected to pin T4 CLK11n 7 4 Power Supply Circuitry The AT91CAP9A DKZ board derives most of the necessary voltages from the motherboard connectors Some service voltage sources are regenerated on board Please look at the appended schematics Section 16 sheets 1 5 9 and 10 for in depth details on power paths 7 5 Memory System memory resources are provided via extensio...

Page 51: ... be pow ered separately thereby allowing different signaling standards of a system to be implemented in parallel Banking Allocations Banks 1 2 and 3 user IO going down to motherboard for user extension PCI64 Mistral connection USB device interfaces Banks 4 5 and 6 partly PISMO II extension connector Bank 6 partly leftovers allocated between the user I O grid and EBI FPGA connector Bank 7 EBI FPGA ...

Page 52: ...A28 AH25 DQSn14B 8 MPIOA29 AH26 DQ14B 8 MPIOA30 AH24 DQ14B 8 MPIOA31 AK25 DQ14B 8 MPIOB00 AJ25 DQS14B 8 MPIOB01 AB20 8 MPIOB02 AE21 8 MPIOB03 AG20 8 MPIOB04 AF20 8 MPIOB05 AM24 DQ13B 8 MPIOB06 AL24 DQSn13B 8 MPIOB07 AK24 DQ13B 8 MPIOB08 AK23 DQ13B 8 MPIOB09 AM23 DQ13B 8 MPIOB10 AL23 DQS13B 8 MPIOB11 AD20 8 MPIOB12 AG23 DQ12B 8 MPIOB13 AH22 DQSn12B 8 MPIOB14 AG22 DQ12B 8 MPIOB15 AK22 DQ12B 8 MPIOB1...

Page 53: ... DQ11B 8 MPIOB27 AM21 DQ11B 8 MPIOB28 AL21 DQS11B 8 MPIOB29 AD19 8 MPIOB30 AE19 8 MPIOB31 AF19 8 MPIOB32 AB18 8 MPIOB33 AH20 DQ10B 8 MPIOB34 AJ20 DQSn10B 8 MPIOB35 AJ19 DQ10B 8 MPIOB36 AH19 DQ10B 8 MPIOB37 AL20 DQ10B 8 MPIOB38 AK20 DQS10B 8 MPIOB39 AC18 8 MPIOB40 AD18 8 MPIOB41 AB17 8 MPIOB42 AC17 8 MPIOB43 AJ17 CLK5n 8 MPIOB44 AL17 CLK4n 8 Table 7 1 MPIO FPGA Signal Assignment Continued CAP MPIO ...

Page 54: ... SODIMM_D03 AK12 DQ7B 7 10 SODIMM_D11 AF12 DQ5B 7 11 VCCIO_7 12 VCCIO_7 13 SODIMM_D04 AM10 DQ6B 7 14 SODIMM_D12 AM9 DQ4B 7 15 SODIMM_D05 AL10 DQ6B 7 16 SODIMM_D13 AJ8 DQ4B 7 17 SODIMM_D06 AH11 DQ6B 7 18 SODIMM_D14 AK8 DQ4B 7 19 SODIMM_D07 AJ11 DQ6B 7 20 SODIMM_D15 AJ10 DQ4B 7 21 GND 22 GND 23 SODIMM_D16 AL8 DQSn3B 7 24 SODIMM_D24 AH8 DQSn1B 7 25 SODIMM_D17 AJ7 DQ3B 7 26 SODIMM_D25 AH7 DQ1B 7 27 VC...

Page 55: ...16 7 50 SODIMM_C28 AB14 7 51 SODIMM_C02 AC15 7 52 SODIMM_C29 AL9 7 53 SODIMM_C03 AM14 DQ9B 7 54 SODIMM_C30 AK9 DQS4B 7 55 GND 56 GND 57 SODIMM_C04 AL13 DQSn9B 7 58 SODIMM_C31 AC13 7 59 SODIMM_C05 AJ13 DQ9B 7 60 SODIMM_C32 AE12 7 61 SODIMM_C06 AJ14 DQ9B 7 62 SODIMM_C33 AM8 DQ3B 7 63 VCCIO_7 64 VCCIO_7 65 SODIMM_C07 AL14 DQ9B 7 66 SODIMM_C34 AL7 DQS3B 7 67 SODIMM_C08 AK13 DQS9B 7 68 SODIMM_C35 AB13 ...

Page 56: ...7 86 SODIMM_C42 AC12 7 87 SODIMM_C16 AG14 DQS8B 7 88 SODIMM_C43 AK5 DQSn0B 7 89 SODIMM_C17 AB15 7 90 SODIMM_C44 AC11 7 91 GND 92 GND 93 SODIMM_C18 AF14 7 94 SODIMM_C45 AB12 7 95 SODIMM_C19 AM12 DQ7B 7 96 SODIMM_C46 AE10 7 97 SODIMM_C20 AL11 DQS7B 7 98 SODIMM_C47 AB11 RDN7 7 99 SODIMM_C21 AC14 7 100 SODIMM_C48 AD10 7 101 VCCIO_7 102 VCCIO_7 103 SODIMM_C22 AK11 DQSn6B 7 104 SODIMM_C49 AE9 7 105 SODI...

Page 57: ...AE1 DIFFIO_RX100p 6 125 SODIMM_S02 AF2 DIFFIO_RX102n 6 126 SODIMM_S12 W11 DIFFIO_TX99n 6 127 SODIMM_S03 AF1 DIFFIO_RX102p 6 128 SODIMM_S13 W10 DIFFIO_TX99p 6 129 VCCIO_6 130 VCCIO_6 131 SODIMM_S04 Y11 DIFFIO_TX101n 6 132 SODIMM_S14 AD2 DIFFIO_RX99n 6 133 SODIMM_S05 Y10 DIFFIO_TX101p 6 134 SODIMM_S15 AD1 DIFFIO_RX99p 6 135 SODIMM_S06 AE4 DIFFIO_RX101n 6 136 SODIMM_S16 Y9 DIFFIO_TX98n 6 137 SODIMM_S...

Page 58: ...D5 D12 DQ7T 4 A05 DM_D30 PISMO_DM_DD6 A11 DQ7T 4 A06 DM_DQS1_DH PISMO_DM_DQSB_DH D7 DQS2T 4 A07 DM_D08 PISMO_DM_DB0 B7 DQ2T 4 A08 DM_D10 PISMO_DM_DB2 E6 DQ2T 4 A09 DM_D12 PISMO_DM_DB4 C9 DQ3T 4 A10 DM_D15 PISMO_DM_DB7 B9 DQSn3T 4 A11 DM_D01 PISMO_DM_DA1 D5 DQ0T 4 A12 DM_D03 PISMO_DM_DA3 A4 DQ0T 4 A13 DM_D05 PISMO_DM_DA5 D6 DQ1T 4 A14 DM_D06 PISMO_DM_DA6 C6 DQ1T 4 A15 DM_DQS0_DH PISMO_DM_DQSA_DH C4...

Page 59: ...SMO_DM_DD4 C12 DQS7T 4 B05 DM_D31 PISMO_DM_DD7 B11 DQ7T 4 B06 DM_DQS1_DL PISMO_DM_DQSB_DL C7 DQSn2T 4 B07 DM_D09 PISMO_DM_DB1 E7 DQ2T 4 B08 DM_D11 PISMO_DM_DB3 A7 DQ2T 4 B09 DM_D13 PISMO_DM_DB5 A8 DQ3T 4 B10 DM_D14 PISMO_DM_DB6 C8 DQ3T 4 B11 DM_D00 PISMO_DM_DA0 B4 DQ0T 4 B12 DM_D02 PISMO_DM_DA2 E5 DQ0T 4 B13 DM_D04 PISMO_DM_DA4 A5 DQ1T 4 B14 DM_D07 PISMO_DM_DA7 B6 DQSn1T 4 B15 DM_DQS0_DL PISMO_DM_...

Page 60: ...DIFFIO_RX75p 5 B38 SM_D09 PISMO_SM56 G2 DIFFIO_RX75n 5 B39 SM_D08 PISMO_SM55 M10 DIFFIO_TX75p 5 B40 DNU15 n c C01 DNU11 n c C02 DM_BA2 PISMO_DM18 L16 4 C03 DM_RESET PISMO_DM35 C13 DQS9T 4 C04 DM_ODT1 PISMO_DM33 H14 4 C05 DM_ODT0 PISMO_DM32 F15 DQ8T 4 C06 DM_VREF see schematics Section 16 C07 DM_VIO_9 VCCIO_4 C08 DM_VIO_3 VCCIO_4 C09 DM_VIO_6 VCCIO_4 C10 DM_VIO_5 VCCIO_4 C11 DM_VIO_8 VCCIO_4 C12 DM...

Page 61: ...SM_VIO_1 VCCIO_5 C37 SM_VIO_0 VCCIO_5 C38 SM_V18_2 1 8V C39 SM_V18_1 PISMO_SM88 D3 INPUT 5 C40 SM_V18_0 PISMO_SM87 D4 INPUT 5 D01 DM_CS1 PISMO_DM27 F14 DQS8T 4 D02 DM_A15 PISMO_DM15 H12 4 D03 DM_A07 PISMO_DM07 L14 4 D04 DM_A11 PISMO_DM11 K13 4 D05 DM_CKE1 PISMO_DM21 K15 4 D06 DM_A14 PISMO_DM14 A9 DQ3T 4 D07 DM_A08 PISMO_DM08 B5 DQS1T 4 D08 DM_DQM1 PISMO_DM29 F13 DQ8T 4 D09 VSS37 GND D10 DM_CLK1_DH...

Page 62: ...SMO_SM14 R5 DIFFIO_TX85n 5 D33 SM_A12 PISMO_SM12 M2 DIFFIO_RX86n 5 D34 SM_A10 PISMO_SM10 R11 DIFFIO_TX86n 5 D35 SM_A08 PISMO_SM08 R3 DIFFIO_RX87n 5 D36 SM_A06 PISMO_SM06 T6 DIFFIO_TX87n 5 D37 SM_A04 PISMO_SM04 P2 DIFFIO_RX88n 5 D38 SM_A02 PISMO_SM02 T11 DIFFIO_TX88n 5 D39 SM_A00 PISMO_SM00 T1 CLK10p DIFFIO_ RX_C3p 5 D40 SM_BE0 PISMO_SM32 L4 DIFFIO_RX81n 5 E01 VSS46 GND E02 DM_A04 PISMO_DM04 H11 4 ...

Page 63: ... SM_A19 PISMO_SM19 R6 DIFFIO_TX84p 5 E29 SM_A17 PISMO_SM17 N2 DIFFIO_RX85p 5 E30 SM_BE2 PISMO_SM34 P9 DIFFIO_TX80n 5 E31 SM_BE3 PISMO_SM35 P8 DIFFIO_TX80p 5 E32 SM_A15 PISMO_SM15 R4 DIFFIO_TX85p 5 E33 SM_A13 PISMO_SM13 M1 DIFFIO_RX86p 5 E34 SM_A11 PISMO_SM11 R10 DIFFIO_TX86p 5 E35 SM_A09 PISMO_SM09 R2 DIFFIO_RX87p 5 E36 SM_A07 PISMO_SM07 T5 DIFFIO_TX87p 5 E37 SM_A05 PISMO_SM05 P1 DIFFIO_RX88p 5 E3...

Page 64: ...IO_6 F27 NA_V33_0 3 3V F28 NA_V18_0 1 8V F29 VSS15 GND F30 VSS14 GND F31 SM_OE PISMO_SM84 H4 DIFFIO_RX68n 5 F32 SM_WE PISMO_SM74 K9 DIFFIO_TX70n 5 F33 SM_LBA PISMO_SM83 J8 DIFFIO_TX68p 5 F34 SM_BUSY PISMO_SM36 K2 DIFFIO_RX80n 5 F35 SM_BWAIT PISMO_SM37 K1 DIFFIO_RX80p 5 F36 VSS4 GND F37 VSS3 GND F38 VSS2 GND F39 VSS1 GND F40 VSS0 GND G01 FS_SO PISMO_FS08 A16 CLK12p 4 G02 FS_SI PISMO_FS07 B16 CLK12n...

Page 65: ...0 AC7 DIFFIO_TX108n 6 G20 NA_IO11 PISMO_NA09 AG3 DIFFIO_RX109p 6 G21 NA_IO10 PISMO_NA08 AG4 DIFFIO_RX109n 6 G22 NA_IO9 PISMO_NA21 AH1 DIFFIO_RX106p 6 G23 NA_IO8 PISMO_NA20 AH2 DIFFIO_RX106n 6 G24 DNU12 n c G25 NA_RY PISMO_NA24 AF4 DIFFIO_RX105n 6 G26 NA_CS2 PISMO_NA04 AH4 DIFFIO_RX110n 6 G27 NA_CS1 PISMO_NA03 AD6 DIFFIO_TX110p 6 G28 NA_CLE PISMO_NA01 AF5 DIFFIO_RX111p 6 G29 NA_WE PISMO_NA25 AF3 DI...

Page 66: ...IFFIO_TX106p 6 H17 NA_IO6 PISMO_NA18 AB8 DIFFIO_TX106n 6 H18 NA_IO5 PISMO_NA17 AE5 DIFFIO_RX107p 6 H19 NA_IO4 PISMO_NA16 AE6 DIFFIO_RX107n 6 H20 NA_IO3 PISMO_NA15 AC8 DIFFIO_TX107p 6 H21 NA_IO2 PISMO_NA14 AC9 DIFFIO_TX107n 6 H22 NA_IO1 PISMO_NA07 AD8 DIFFIO_TX109p 6 H23 NA_IO0 PISMO_NA06 AD9 DIFFIO_TX109n 6 H24 NA_PRE PISMO_NA22 AB10 DIFFIO_TX105n 6 H25 NA_RE PISMO_NA23 AB9 DIFFIO_TX105p 6 H26 NA_...

Page 67: ...RID50 59 Column G UGRID60 69 Column H UGRID70 75 3 3V 3 3V GND GND H36 DNU2 n c H37 SM_CS3 PISMO_SM46 M7 DIFFIO_TX77n 5 H38 SM_CS2 PISMO_SM45 J1 DIFFIO_RX78p 5 H39 SM_CS1 PISMO_SM44 J2 DIFFIO_RX78n 5 H40 SM_CS0 PISMO_SM43 N6 DIFFIO_TX78p 5 Table 7 3 PISMO FPGA Signal Assignment Continued PISMO Pin Standard PISMO Name Board Signal Name FPGA Pin Alternate FPGA Pin Function FPGA Bank Table 7 4 I O Gr...

Page 68: ...1 UGRID26 B6 IO DIFFIO_TX96n W5 UGRID27 B6 IO DIFFIO_TX96p W4 UGRID28 B6 IO DIFFIO_RX96n AB4 UGRID29 B6 IO DIFFIO_RX96p AB3 UGRID30 B6 IO DIFFIO_TX95n W7 UGRID31 B6 IO DIFFIO_TX95p W6 UGRID32 B6 IO DIFFIO_RX95n AB2 UGRID33 B6 IO DIFFIO_RX95p AB1 UGRID34 B6 IO DIFFIO_TX94n W9 UGRID35 B6 IO DIFFIO_TX94p W8 UGRID36 B6 IO DIFFIO_RX94n Y5 UGRID37 B6 IO DIFFIO_RX94p Y4 UGRID38 B6 IO DIFFIO_TX93n V5 UGRI...

Page 69: ...S5 right B6 CLK9n INPUT U4 UGRID59 1 B6 CLK9p INPUT U3 UGRID60 1 B6 IO CLK8n DIFFIO_RX_C2n U2 UGRID61 B6 IO CLK8p DIFFIO_RX_C2p U1 UGRID62 B9 IO PLL5_FBn OUT2n E15 UGRID63 B9 IO PLL5_FBp OUT2p D15 UGRID64 B9 IO PLL5_OUT0n C15 UGRID65 B9 IO PLL5_OUT0p B15 UGRID66 B9 IO PLL5_OUT1n D16 UGRID67 B9 IO PLL5_OUT1p C16 UGRID68 B11 IO PLL11_OUT0p B18 UGRID69 B11 IO PLL11_OUT0n C18 UGRID70 B11 IO PLL11_OUT1...

Page 70: ...VCCINT K23 1V2 VCCINT M21 1V2 VCCINT N13 1V2 VCCINT N15 1V2 VCCINT N17 1V2 VCCINT N19 1V2 VCCINT P14 1V2 VCCINT P16 1V2 VCCINT P18 1V2 VCCINT P20 1V2 VCCINT R13 1V2 VCCINT R15 1V2 VCCINT R17 1V2 VCCINT R19 1V2 VCCINT T14 1V2 VCCINT T16 1V2 VCCINT T18 1V2 VCCINT T20 1V2 VCCINT U13 1V2 VCCINT U15 1V2 VCCINT U17 1V2 VCCINT U19 1V2 VCCINT V14 1V2 VCCINT V16 1V2 VCCINT V18 1V2 VCCINT V20 1V2 VCCINT W13...

Page 71: ...D2 N21 3V3 VCCPD5 R12 3V3 VCCPD2 R21 3V3 VCCPD6 V12 3V3 VCCPD1 V21 3V3 VCCPD6 Y12 3V3 VCCPD1 Y21 3V3 GND A13 GND GND A2 GND GND A20 GND GND A31 GND GND AA14 GND GND AA19 GND GND AA21 GND GND AB22 GND GND AC28 GND GND AC5 GND GNDA_PLL6 AD16 GND GNDA_PLL12 AD17 GND GNDA_PLL6 AE16 GND GNDA_PLL12 AE17 GND GND AF17 GND GNDA_PLL9 AF7 GND Table 7 5 FPGA Pins Sorted by Bank Signal Name Continued Bank Pin ...

Page 72: ...D GND B1 GND TEMPDIODEn B3 GND GND B32 GND GND E10 GND GND E23 GND GNDA_PLL7 F26 GND GND F27 GND GND F7 GND GNDA_PLL5 G16 GND GND G17 GND GNDA_PLL11 G18 GND GNDA_PLL7 G26 GND GNDA_PLL10 G7 GND GNDA_PLL10 G8 GND TEMPDIODEp G9 GND GNDA_PLL5 H16 GND GNDA_PLL11 H18 GND GND J24 GND GND K28 GND GND K5 GND GND L11 GND GND M12 GND Table 7 5 FPGA Pins Sorted by Bank Signal Name Continued Bank Pin Type Name...

Page 73: ...D R14 GND GND R16 GND GND R18 GND GND R20 GND GNDA_PLL4 R8 GND GND T13 GND GND T15 GND GND T17 GND GND T19 GND GNDA_PLL1 T25 GND GNDA_PLL1 T26 GND GND T7 GND GNDA_PLL4 T8 GND GND U14 GND GND U16 GND GND U18 GND GND U20 GND GNDA_PLL2 U25 GND GNDA_PLL2 U26 GND GNDA_PLL3 U8 GND GND V11 GND GND V13 GND Table 7 5 FPGA Pins Sorted by Bank Signal Name Continued Bank Pin Type Name Other Pin Information Co...

Page 74: ...PLL12 AF18 VCCA_PLL VCCA_PLL8 AF26 VCCA_PLL VCCA_PLL5 G15 VCCA_PLL VCCA_PLL11 H17 VCCA_PLL VCCA_PLL7 H26 VCCA_PLL VCCA_PLL10 H8 VCCA_PLL VCCA_PLL4 R9 VCCA_PLL VCCA_PLL1 T24 VCCA_PLL VCCA_PLL3 U9 VCCA_PLL VCCA_PLL2 V26 VCCA_PLL VCCD_PLL6 AD15 VCCD_PLL VCCD_PLL12 AE18 VCCD_PLL VCCD_PLL9 AE8 VCCD_PLL VCCD_PLL8 AF25 VCCD_PLL VCCD_PLL5 H15 VCCD_PLL VCCD_PLL7 H25 VCCD_PLL VCCD_PLL10 H7 VCCD_PLL Table 7 ...

Page 75: ...VCCIO3 A30 VCCIO_3 VCCIO3 E21 VCCIO_3 VCCIO3 M17 VCCIO_3 VCCIO4 A15 VCCIO_4 VCCIO4 A3 VCCIO_4 VCCIO4 E12 VCCIO_4 VCCIO4 M16 VCCIO_4 VCCIO5 C1 VCCIO_5 VCCIO5 M5 VCCIO_5 VCCIO5 R1 VCCIO_5 VCCIO5 T12 VCCIO_5 VCCIO6 AA5 VCCIO_6 VCCIO6 AK1 VCCIO_6 VCCIO6 U12 VCCIO_6 VCCIO6 V1 VCCIO_6 VCCIO7 AA16 VCCIO_7 VCCIO7 AH12 VCCIO_7 VCCIO7 AM15 VCCIO_7 VCCIO7 AM3 VCCIO_7 VCCIO8 AA17 VCCIO_8 VCCIO8 AH21 VCCIO_8 V...

Page 76: ...GA21 B1 IO DIFFIO_TX24p W29 FPGA22 B1 IO DIFFIO_TX24n W28 FPGA23 B1 IO DIFFIO_RX23p AA30 FPGA24 B1 IO DIFFIO_RX23n AA29 FPGA25 B1 IO DIFFIO_TX23p W27 FPGA26 B1 IO DIFFIO_TX23n W26 FPGA27 B1 IO DIFFIO_RX22p Y29 FPGA28 B1 IO DIFFIO_RX22n Y28 FPGA29 B1 CLK3n INPUT U29 FPGA3 B1 IO DIFFIO_TX22p W25 FPGA30 B1 IO DIFFIO_TX22n W24 FPGA31 B1 IO DIFFIO_RX21p AB30 FPGA32 B1 IO DIFFIO_RX21n AB29 FPGA33 B1 IO ...

Page 77: ...A54 B1 IO DIFFIO_TX16n AC26 FPGA55 B1 IO DIFFIO_RX15p AG32 FPGA56 B1 IO DIFFIO_RX15n AG31 FPGA57 B1 IO DIFFIO_TX15p Y23 FPGA58 B1 IO DIFFIO_TX15n Y22 FPGA59 B1 IO DIFFIO_TX28p U23 FPGA6 B1 IO DIFFIO_RX14p AC30 FPGA60 B1 IO DIFFIO_RX14n AC29 FPGA61 B1 IO DIFFIO_TX14p AA25 FPGA62 B1 IO DIFFIO_TX14n AA24 FPGA63 B1 IO DIFFIO_RX13p AD30 FPGA64 B1 IO DIFFIO_RX13n AD29 FPGA65 B1 IO DIFFIO_TX13p AB26 FPGA...

Page 78: ...O DIFFIO_RX7p AH30 FPGA88 B1 IO DIFFIO_RX7n AH29 FPGA89 B1 IO DIFFIO_RX27n W31 FPGA9 B1 IO DIFFIO_TX7p AE28 FPGA90 B1 IO DIFFIO_TX7n AE27 FPGA91 B1 IO DIFFIO_RX6p AF28 FPGA92 B1 IO DIFFIO_RX6n AF27 FPGA93 B1 FPLL8CLKn INPUT AJ29 FPGA94 B1 FPLL8CLKp INPUT AJ30 FPGA95 B1 VREFB1N1 VREFB1N1 AD28 VREFB1 B1 VREFB1N2 VREFB1N2 AG28 VREFB1 B1 VREFB1N0 VREFB1N0 W30 VREFB1 B10 IO PLL6_OUT1p AJ15 UGRID14 B10 ...

Page 79: ...0p H28 FPGA102 B2 IO DIFFIO_TX50n H27 FPGA103 B2 IO DIFFIO_RX49p E30 FPGA104 B2 IO DIFFIO_RX49n E29 FPGA105 B2 IO DIFFIO_TX49p K27 FPGA106 B2 IO DIFFIO_TX49n K26 FPGA107 B2 IO DIFFIO_RX48p D32 FPGA108 B2 IO DIFFIO_RX48n D31 FPGA109 B2 IO DIFFIO_TX48p J27 FPGA110 B2 IO DIFFIO_TX48n J26 FPGA111 B2 IO DIFFIO_RX47p F30 FPGA112 B2 IO DIFFIO_RX47n F29 FPGA113 B2 IO DIFFIO_TX47p L28 FPGA114 B2 IO DIFFIO_...

Page 80: ...138 B2 IO DIFFIO_TX41n N24 FPGA139 B2 IO DIFFIO_RX40p H32 FPGA140 B2 IO DIFFIO_RX40n H31 FPGA141 B2 IO DIFFIO_TX40p N23 FPGA142 B2 IO DIFFIO_TX40n N22 FPGA143 B2 IO DIFFIO_RX39p J32 FPGA144 B2 IO DIFFIO_RX39n J31 FPGA145 B2 IO DIFFIO_TX39p P23 FPGA146 B2 IO DIFFIO_TX39n P22 FPGA147 B2 IO DIFFIO_RX38p K30 FPGA148 B2 IO DIFFIO_RX38n K29 FPGA149 B2 IO DIFFIO_TX38p N27 FPGA150 B2 IO DIFFIO_TX38n N26 F...

Page 81: ...4 B2 CLK1p INPUT T30 FPGA175 B2 IO DIFFIO_RX31p M32 FPGA176 B2 IO DIFFIO_RX31n M31 FPGA177 B2 IO DIFFIO_TX31p R29 FPGA178 B2 IO DIFFIO_TX31n R28 FPGA179 B2 IO DIFFIO_RX30p P32 FPGA180 B2 IO DIFFIO_RX30n P31 FPGA181 B2 IO DIFFIO_TX30p T28 FPGA182 B2 IO DIFFIO_TX30n T27 FPGA183 B2 IO DIFFIO_RX29p R31 FPGA184 B2 IO DIFFIO_RX29n R30 FPGA185 B2 IO DIFFIO_TX29p T23 FPGA186 B2 IO DIFFIO_TX29n T22 FPGA187...

Page 82: ... B3 IO PGM1 F19 FPGA198 B3 IO PGM0 E17 FPGA199 B3 IO CRC_ERROR G20 FPGA200 B3 IO DATA1 F20 FPGA201 B3 IO DQS10T D19 FPGA202 B3 IO DQ10T B20 FPGA203 B3 IO DQ10T E19 FPGA204 B3 IO DQ10T C20 FPGA205 B3 IO DQSn10T D20 FPGA206 B3 IO DQ10T E20 FPGA207 B3 IO L19 FPGA208 B3 IO L18 FPGA209 B3 IO J19 FPGA210 B3 IO K19 FPGA211 B3 IO DQS11T B21 FPGA212 B3 IO DQ11T A21 FPGA213 B3 IO DQ11T C21 FPGA214 B3 IO DQ1...

Page 83: ...3 IO K21 FPGA235 B3 IO H21 FPGA236 B3 IO J21 FPGA237 B3 IO DQS14T B25 FPGA238 B3 IO DQ14T A25 FPGA239 B3 IO DQ14T A26 FPGA240 B3 IO DQ14T D26 FPGA241 B3 IO DQSn14T B26 FPGA242 B3 IO DQ14T C26 FPGA243 B3 IO G21 FPGA244 B3 IO DQS15T D25 FPGA245 B3 IO DQ15T E24 FPGA246 B3 IO DQ15T C25 FPGA247 B3 IO DQ15T E27 FPGA248 B3 IO DQSn15T E25 FPGA249 B3 IO DQ15T E26 FPGA250 B3 IO F21 FPGA251 B3 IO DQS16T B27 ...

Page 84: ...GA272 B3 IO DATA6 F24 FPGA273 B3 IO DATA7 G24 FPGA274 B3 IO RDYnBSY H24 FPGA275 B3 nCE nCE C30 NCE B3 IO nCSO G19 NCSO B3 nSTATUS nSTATUS B30 NSTATUS B3 IO INIT_DONE G25 UGRID75 B3 VREFB3N0 VREFB3N0 C19 VREFB3 B3 VREFB3N2 VREFB3N2 C31 VREFB3 B3 VREFB3N1 VREFB3N1 D24 VREFB3 B4 MSEL0 MSEL0 B2 MSEL0 B4 MSEL1 MSEL1 F6 MSEL1 B4 MSEL2 MSEL2 J10 MSEL2 B4 MSEL3 MSEL3 H10 MSEL3 B4 IO CLK13p E16 PISMO_AUX12...

Page 85: ...DC2 B4 IO DQ4T F10 PISMO_DM_DC3 B4 IO DQS5T C10 PISMO_DM_DC4 B4 IO DQ5T A10 PISMO_DM_DC5 B4 IO DQ5T B10 PISMO_DM_DC6 B4 IO DQ5T D10 PISMO_DM_DC7 B4 IO DQ6T E11 PISMO_DM_DD0 B4 IO DQ6T G10 PISMO_DM_DD1 B4 IO DQ6T G11 PISMO_DM_DD2 B4 IO DQ6T G12 PISMO_DM_DD3 B4 IO DQS7T C12 PISMO_DM_DD4 B4 IO DQ7T D12 PISMO_DM_DD5 B4 IO DQ7T A11 PISMO_DM_DD6 B4 IO DQ7T B11 PISMO_DM_DD7 B4 IO DQS0T C4 PISMO_DM_DQSA_ ...

Page 86: ... C11 PISMO_DM19 B4 IO RUP4 L12 PISMO_DM2 B4 IO DQ5T D11 PISMO_DM20 B4 IO K15 PISMO_DM21 B4 IO H13 PISMO_DM22 B4 IO J14 PISMO_DM23 B4 IO DQSn7T B12 PISMO_DM24 B4 IO DQ7T A12 PISMO_DM25 B4 IO G14 PISMO_DM26 B4 IO DQS8T F14 PISMO_DM27 B4 IO DQ8T E13 PISMO_DM28 B4 IO DQ8T F13 PISMO_DM29 B4 IO RDN4 K11 PISMO_DM3 B4 IO DQ8T G13 PISMO_DM30 B4 IO DQSn8T E14 PISMO_DM31 B4 IO DQ8T F15 PISMO_DM32 B4 IO H14 P...

Page 87: ... VREFB4 B4 VREFB4N1 VREFB4N1 D9 VREFB4 B5 CLK11n INPUT T4 EXT_CLK B5 IO DIFFIO_TX66n H6 PISMO_AUX10 B5 IO DIFFIO_TX66p H5 PISMO_AUX11 B5 IO DIFFIO_TX67p J6 PISMO_AUX7 B5 IO DIFFIO_RX67n G6 PISMO_AUX8 B5 IO DIFFIO_RX67p G5 PISMO_AUX9 B5 IO CLK10p DIFFIO_RX_C3p T1 PISMO_SM0 B5 IO CLK10n DIFFIO_RX_C3n T2 PISMO_SM1 B5 IO DIFFIO_TX86n R11 PISMO_SM10 B5 IO DIFFIO_TX86p R10 PISMO_SM11 B5 IO DIFFIO_RX86n ...

Page 88: ...1 B5 IO DIFFIO_RX81n L4 PISMO_SM32 B5 IO DIFFIO_RX81p L3 PISMO_SM33 B5 IO DIFFIO_TX80n P9 PISMO_SM34 B5 IO DIFFIO_TX80p P8 PISMO_SM35 B5 IO DIFFIO_RX80n K2 PISMO_SM36 B5 IO DIFFIO_RX80p K1 PISMO_SM37 B5 IO DIFFIO_TX79n N9 PISMO_SM38 B5 IO DIFFIO_TX79p N8 PISMO_SM39 B5 IO DIFFIO_RX88n P2 PISMO_SM4 B5 IO DIFFIO_RX79n K4 PISMO_SM40 B5 IO DIFFIO_RX79p K3 PISMO_SM41 B5 IO DIFFIO_TX78n N7 PISMO_SM42 B5 ...

Page 89: ...4 B5 IO DIFFIO_RX73p F1 PISMO_SM65 B5 IO DIFFIO_TX72n L10 PISMO_SM66 B5 IO DIFFIO_TX72p L9 PISMO_SM67 B5 IO DIFFIO_RX72n F4 PISMO_SM68 B5 IO DIFFIO_RX72p F3 PISMO_SM69 B5 IO DIFFIO_TX87p T5 PISMO_SM7 B5 IO DIFFIO_TX71n L8 PISMO_SM70 B5 IO DIFFIO_TX71p L7 PISMO_SM71 B5 IO DIFFIO_RX71n E2 PISMO_SM72 B5 IO DIFFIO_RX71p E1 PISMO_SM73 B5 IO DIFFIO_TX70n K9 PISMO_SM74 B5 IO DIFFIO_TX70p K8 PISMO_SM75 B5...

Page 90: ... AD4 PISMO_AUX5 B6 IO DIFFIO_RX103p AD3 PISMO_AUX6 B6 IO DIFFIO_RX111n AF6 PISMO_NA0 B6 IO DIFFIO_RX111p AF5 PISMO_NA1 B6 IO DIFFIO_TX108n AC7 PISMO_NA10 B6 IO DIFFIO_TX108p AC6 PISMO_NA11 B6 IO DIFFIO_RX108n AJ2 PISMO_NA12 B6 IO DIFFIO_RX108p AJ1 PISMO_NA13 B6 IO DIFFIO_TX107n AC9 PISMO_NA14 B6 IO DIFFIO_TX107p AC8 PISMO_NA15 B6 IO DIFFIO_RX107n AE6 PISMO_NA16 B6 IO DIFFIO_RX107p AE5 PISMO_NA17 B...

Page 91: ...AD2 SODIMM_S14 B6 IO DIFFIO_RX99p AD1 SODIMM_S15 B6 IO DIFFIO_TX98n Y9 SODIMM_S16 B6 IO DIFFIO_TX98p Y8 SODIMM_S17 B6 IO DIFFIO_RX98n AC4 SODIMM_S18 B6 IO DIFFIO_RX102n AF2 SODIMM_S2 B6 IO DIFFIO_RX102p AF1 SODIMM_S3 B6 IO DIFFIO_TX101n Y11 SODIMM_S4 B6 IO DIFFIO_TX101p Y10 SODIMM_S5 B6 IO DIFFIO_RX101n AE4 SODIMM_S6 B6 IO DIFFIO_RX101p AE3 SODIMM_S7 B6 IO DIFFIO_TX100n AA7 SODIMM_S8 B6 IO DIFFIO_...

Page 92: ...3 B6 IO DIFFIO_TX92p V6 UGRID44 B6 IO DIFFIO_RX92n AA2 UGRID45 B6 IO DIFFIO_RX92p AA1 UGRID46 B6 IO DIFFIO_TX91n V10 UGRID47 B6 IO DIFFIO_TX91p V9 UGRID48 B6 IO DIFFIO_RX91n Y3 UGRID49 B6 IO DIFFIO_RX91p Y2 UGRID50 B6 IO DIFFIO_TX90n U11 UGRID51 B6 IO DIFFIO_TX90p U10 UGRID52 B6 IO DIFFIO_RX90n W2 UGRID53 B6 IO DIFFIO_RX90p W1 UGRID54 B6 IO DIFFIO_TX89n U6 UGRID55 B6 IO DIFFIO_TX89p U5 UGRID56 B6 ...

Page 93: ... SODIMM_C16 B7 IO AB15 SODIMM_C17 B7 IO AF14 SODIMM_C18 B7 IO DQ7B AM12 SODIMM_C19 B7 IO AC15 SODIMM_C2 B7 IO DQS7B AL11 SODIMM_C20 B7 IO AC14 SODIMM_C21 B7 IO DQSn6B AK11 SODIMM_C22 B7 IO DQS6B AK10 SODIMM_C23 B7 IO AD13 SODIMM_C24 B7 IO AE13 SODIMM_C25 B7 IO DQ5B AG12 SODIMM_C26 B7 IO DQS5B AF11 SODIMM_C27 B7 IO AB14 SODIMM_C28 B7 IO DQSn4B AL9 SODIMM_C29 B7 IO DQ9B AM14 SODIMM_C3 B7 IO DQS4B AK...

Page 94: ...O CLK7p AH16 SODIMM_C50 B7 IO CLK7n AG16 SODIMM_C51 B7 IO CLK6p AM16 SODIMM_C52 B7 IO CLK6n AL16 SODIMM_C53 B7 IO DQ9B AJ14 SODIMM_C6 B7 IO DQ9B AL14 SODIMM_C7 B7 IO DQS9B AK13 SODIMM_C8 B7 IO AD14 SODIMM_C9 B7 IO DQSn7B AL12 SODIMM_D0 B7 IO DQ7B AM11 SODIMM_D1 B7 IO DQ5B AG10 SODIMM_D10 B7 IO DQ5B AF12 SODIMM_D11 B7 IO DQ4B AM9 SODIMM_D12 B7 IO DQ4B AJ8 SODIMM_D13 B7 IO DQ4B AK8 SODIMM_D14 B7 IO ...

Page 95: ...Q6B AL10 SODIMM_D5 B7 IO DQ6B AH11 SODIMM_D6 B7 IO DQ6B AJ11 SODIMM_D7 B7 IO DQSn5B AG11 SODIMM_D8 B7 IO DQ5B AF10 SODIMM_D9 B7 IO DQS0B AK4 SODIMM_DQS0 B7 IO DQS2B AL5 SODIMM_DQS1 B7 VREFB7N1 VREFB7N1 AJ9 VREFB7 B7 VREFB7N0 VREFB7N0 AK14 VREFB7 B7 VREFB7N2 VREFB7N2 AK2 VREFB7 B8 IO AG25 MPIOA0 B8 IO AB21 MPIOA1 B8 IO DQS17B AK28 MPIOA10 B8 IO AC21 MPIOA11 B8 IO AG21 MPIOA12 B8 IO DQ16B AK27 MPIOA...

Page 96: ...OA31 B8 IO AD22 MPIOA4 B8 IO DQ17B AH28 MPIOA5 B8 IO DQSn17B AK29 MPIOA6 B8 IO DQ17B AJ28 MPIOA7 B8 IO DQ17B AM29 MPIOA8 B8 IO DQ17B AL29 MPIOA9 B8 IO DQS14B AJ25 MPIOB0 B8 IO AB20 MPIOB1 B8 IO DQS13B AL23 MPIOB10 B8 IO AD20 MPIOB11 B8 IO DQ12B AG23 MPIOB12 B8 IO DQSn12B AH22 MPIOB13 B8 IO DQ12B AG22 MPIOB14 B8 IO DQ12B AK22 MPIOB15 B8 IO DQ12B AJ23 MPIOB16 B8 IO DQS12B AJ22 MPIOB17 B8 IO AC20 MPI...

Page 97: ...O DQ10B AH19 MPIOB36 B8 IO DQ10B AL20 MPIOB37 B8 IO DQS10B AK20 MPIOB38 B8 IO AC18 MPIOB39 B8 IO AF20 MPIOB4 B8 IO AD18 MPIOB40 B8 IO AB17 MPIOB41 B8 IO AC17 MPIOB42 B8 IO CLK5n AJ17 MPIOB43 B8 IO CLK4n AL17 MPIOB44 B8 IO DQ13B AM24 MPIOB5 B8 IO DQSn13B AL24 MPIOB6 B8 IO DQ13B AK24 MPIOB7 B8 IO DQ13B AK23 MPIOB8 B8 IO DQ13B AM23 MPIOB9 B8 nCONFIG nCONFIG AL30 NCONFIG B8 IO CLK5p AK17 NRST B8 TCK T...

Page 98: ...B9 IO PLL5_FBp OUT2p D15 UGRID64 B9 IO PLL5_OUT0n C15 UGRID65 B9 IO PLL5_OUT0p B15 UGRID66 B9 IO PLL5_OUT1n D16 UGRID67 B9 IO PLL5_OUT1p C16 UGRID68 B9 VCC_PLL5_OUT J16 VCC_PLL5 Table 7 6 FPGA Pins Sorted by Signal Name Bank Pin Type Name Other Pin Information Configuration Function Ball Board Net VCCINT AA12 1V2 VCCINT AC10 1V2 VCCINT K10 1V2 VCCINT K23 1V2 VCCINT M21 1V2 VCCINT N13 1V2 VCCINT N1...

Page 99: ...4 1V2 VCCINT V16 1V2 VCCINT V18 1V2 VCCINT V20 1V2 VCCINT W13 1V2 VCCINT W15 1V2 VCCINT W17 1V2 VCCINT W19 1V2 VCCINT W21 1V2 VCCINT Y14 1V2 VCCINT Y16 1V2 VCCINT Y18 1V2 VCCINT Y20 1V2 VCCPD7 AA13 3V3 VCCPD7 AA15 3V3 VCCPD8 AA18 3V3 VCCPD8 AA20 3V3 VCCPD4 M13 3V3 VCCPD4 M15 3V3 VCCPD3 M18 3V3 VCCPD3 M20 3V3 VCCPD5 N12 3V3 VCCPD2 N21 3V3 Table 7 6 FPGA Pins Sorted by Signal Name Continued Bank Pin...

Page 100: ... H27 FPGA103 B2 IO DIFFIO_RX49p E30 FPGA104 B2 IO DIFFIO_RX49n E29 FPGA105 B2 IO DIFFIO_TX49p K27 FPGA106 B2 IO DIFFIO_TX49n K26 FPGA107 B2 IO DIFFIO_RX48p D32 FPGA108 B2 IO DIFFIO_RX48n D31 FPGA109 B1 IO DIFFIO_TX27n U27 FPGA11 B2 IO DIFFIO_TX48p J27 FPGA110 B2 IO DIFFIO_TX48n J26 FPGA111 B2 IO DIFFIO_RX47p F30 FPGA112 B2 IO DIFFIO_RX47n F29 FPGA113 B2 IO DIFFIO_TX47p L28 FPGA114 B2 IO DIFFIO_TX4...

Page 101: ...PGA134 B2 IO DIFFIO_TX42n M26 FPGA135 B2 IO DIFFIO_RX41p G32 FPGA136 B2 IO DIFFIO_RX41n G31 FPGA137 B2 IO DIFFIO_TX41p N25 FPGA138 B2 IO DIFFIO_TX41n N24 FPGA139 B1 IO DIFFIO_TX26p V29 FPGA14 B2 IO DIFFIO_RX40p H32 FPGA140 B2 IO DIFFIO_RX40n H31 FPGA141 B2 IO DIFFIO_TX40p N23 FPGA142 B2 IO DIFFIO_TX40n N22 FPGA143 B2 IO DIFFIO_RX39p J32 FPGA144 B2 IO DIFFIO_RX39n J31 FPGA145 B2 IO DIFFIO_TX39p P23...

Page 102: ... FPGA167 B2 IO DIFFIO_RX33p L32 FPGA168 B2 IO DIFFIO_RX33n L31 FPGA169 B1 IO DIFFIO_RX25n Y30 FPGA17 B2 IO DIFFIO_TX33p R23 FPGA170 B2 IO DIFFIO_TX33n R22 FPGA171 B2 IO DIFFIO_RX32p N31 FPGA172 B2 IO DIFFIO_RX32n N30 FPGA173 B2 IO DIFFIO_TX32p R25 FPGA174 B2 CLK1p INPUT T30 FPGA175 B2 IO DIFFIO_RX31p M32 FPGA176 B2 IO DIFFIO_RX31n M31 FPGA177 B2 IO DIFFIO_TX31p R29 FPGA178 B2 IO DIFFIO_TX31n R28 F...

Page 103: ...3 IO PGM0 E17 FPGA199 B1 CLK3p INPUT U30 FPGA2 B1 IO DIFFIO_RX24p AB32 FPGA20 B3 IO CRC_ERROR G20 FPGA200 B3 IO DATA1 F20 FPGA201 B3 IO DQS10T D19 FPGA202 B3 IO DQ10T B20 FPGA203 B3 IO DQ10T E19 FPGA204 B3 IO DQ10T C20 FPGA205 B3 IO DQSn10T D20 FPGA206 B3 IO DQ10T E20 FPGA207 B3 IO L19 FPGA208 B3 IO L18 FPGA209 B1 IO DIFFIO_RX24n AB31 FPGA21 B3 IO J19 FPGA210 B3 IO K19 FPGA211 B3 IO DQS11T B21 FPG...

Page 104: ...T C23 FPGA231 B3 IO DQ13T C24 FPGA232 B3 IO DQSn13T B24 FPGA233 B3 IO DQ13T A24 FPGA234 B3 IO K21 FPGA235 B3 IO H21 FPGA236 B3 IO J21 FPGA237 B3 IO DQS14T B25 FPGA238 B3 IO DQ14T A25 FPGA239 B1 IO DIFFIO_RX23p AA30 FPGA24 B3 IO DQ14T A26 FPGA240 B3 IO DQ14T D26 FPGA241 B3 IO DQSn14T B26 FPGA242 B3 IO DQ14T C26 FPGA243 B3 IO G21 FPGA244 B3 IO DQS15T D25 FPGA245 B3 IO DQ15T E24 FPGA246 B3 IO DQ15T C...

Page 105: ...B3 IO DQ17T E28 FPGA265 B3 IO K22 FPGA266 B3 IO F25 FPGA267 B3 IO G22 FPGA268 B3 IO DATA2 G23 FPGA269 B1 IO DIFFIO_TX23n W26 FPGA27 B3 IO DATA3 H23 FPGA270 B3 IO DATA4 J23 FPGA271 B3 IO DATA5 L22 FPGA272 B3 IO DATA6 F24 FPGA273 B3 IO DATA7 G24 FPGA274 B3 IO RDYnBSY H24 FPGA275 B1 IO DIFFIO_RX22p Y29 FPGA28 B1 IO DIFFIO_RX22n Y28 FPGA29 B1 CLK3n INPUT U29 FPGA3 B1 IO DIFFIO_TX22p W25 FPGA30 B1 IO D...

Page 106: ...PGA49 B1 IO DIFFIO_RX28n V30 FPGA5 B1 IO DIFFIO_TX17p AD27 FPGA50 B1 IO DIFFIO_TX17n AD26 FPGA51 B1 IO DIFFIO_RX16p AF32 FPGA52 B1 IO DIFFIO_RX16n AF31 FPGA53 B1 IO DIFFIO_TX16p AC27 FPGA54 B1 IO DIFFIO_TX16n AC26 FPGA55 B1 IO DIFFIO_RX15p AG32 FPGA56 B1 IO DIFFIO_RX15n AG31 FPGA57 B1 IO DIFFIO_TX15p Y23 FPGA58 B1 IO DIFFIO_TX15n Y22 FPGA59 B1 IO DIFFIO_TX28p U23 FPGA6 B1 IO DIFFIO_RX14p AC30 FPGA...

Page 107: ...FFIO_RX9n AF29 FPGA81 B1 IO DIFFIO_TX9p AD25 FPGA82 B1 IO DIFFIO_TX9n AD24 FPGA83 B1 IO DIFFIO_RX8p AG30 FPGA84 B1 IO DIFFIO_RX8n AG29 FPGA85 B1 IO DIFFIO_TX8p AE26 FPGA86 B1 IO DIFFIO_TX8n AE25 FPGA87 B1 IO DIFFIO_RX7p AH30 FPGA88 B1 IO DIFFIO_RX7n AH29 FPGA89 B1 IO DIFFIO_RX27n W31 FPGA9 B1 IO DIFFIO_TX7p AE28 FPGA90 B1 IO DIFFIO_TX7n AE27 FPGA91 B1 IO DIFFIO_RX6p AF28 FPGA92 B1 IO DIFFIO_RX6n A...

Page 108: ...ND GND AF17 GND GNDA_PLL9 AF7 GND GND AF9 GND GNDA_PLL8 AG26 GND GNDA_PLL8 AG27 GND GND AG6 GND GNDA_PLL9 AG7 GND GND AH10 GND GND AH23 GND GND AH27 GND GND AL1 GND GND AL32 GND GND AM13 GND GND AM2 GND GND AM20 GND GND AM31 GND GND B1 GND TEMPDIODEn B3 GND GND B32 GND GND E10 GND GND E23 GND GNDA_PLL7 F26 GND GND F27 GND Table 7 6 FPGA Pins Sorted by Signal Name Continued Bank Pin Type Name Other...

Page 109: ...24 GND GND K28 GND GND K5 GND GND L11 GND GND M12 GND GND M14 GND GND M19 GND GND N1 GND GND N14 GND GND N16 GND GND N18 GND GND N20 GND GND N32 GND GND P12 GND GND P13 GND GND P15 GND GND P17 GND GND P19 GND GND P21 GND GND R14 GND GND R16 GND GND R18 GND GND R20 GND GNDA_PLL4 R8 GND GND T13 GND GND T15 GND Table 7 6 FPGA Pins Sorted by Signal Name Continued Bank Pin Type Name Other Pin Informati...

Page 110: ...8 GND GND V11 GND GND V13 GND GND V15 GND GND V17 GND GND V19 GND GND V22 GND GND V27 GND GNDA_PLL3 V8 GND GND W12 GND GND W14 GND GND W16 GND GND W18 GND GND W20 GND GND Y1 GND GND Y13 GND GND Y15 GND GND Y17 GND GND Y19 GND GND Y32 GND B8 IO AG25 MPIOA0 B8 IO AB21 MPIOA1 B8 IO DQS17B AK28 MPIOA10 B8 IO AC21 MPIOA11 Table 7 6 FPGA Pins Sorted by Signal Name Continued Bank Pin Type Name Other Pin ...

Page 111: ...5 B8 IO AD21 MPIOA26 B8 IO DQ14B AG24 MPIOA27 B8 IO DQSn14B AH25 MPIOA28 B8 IO DQ14B AH26 MPIOA29 B8 IO AF22 MPIOA3 B8 IO DQ14B AH24 MPIOA30 B8 IO DQ14B AK25 MPIOA31 B8 IO AD22 MPIOA4 B8 IO DQ17B AH28 MPIOA5 B8 IO DQSn17B AK29 MPIOA6 B8 IO DQ17B AJ28 MPIOA7 B8 IO DQ17B AM29 MPIOA8 B8 IO DQ17B AL29 MPIOA9 B8 IO DQS14B AJ25 MPIOB0 B8 IO AB20 MPIOB1 B8 IO DQS13B AL23 MPIOB10 B8 IO AD20 MPIOB11 B8 IO ...

Page 112: ...B29 B8 IO AG20 MPIOB3 B8 IO AE19 MPIOB30 B8 IO AF19 MPIOB31 B8 IO AB18 MPIOB32 B8 IO DQ10B AH20 MPIOB33 B8 IO DQSn10B AJ20 MPIOB34 B8 IO DQ10B AJ19 MPIOB35 B8 IO DQ10B AH19 MPIOB36 B8 IO DQ10B AL20 MPIOB37 B8 IO DQS10B AK20 MPIOB38 B8 IO AC18 MPIOB39 B8 IO AF20 MPIOB4 B8 IO AD18 MPIOB40 B8 IO AB17 MPIOB41 B8 IO AC17 MPIOB42 B8 IO CLK5n AJ17 MPIOB43 B8 IO CLK4n AL17 MPIOB44 B8 IO DQ13B AM24 MPIOB5 ...

Page 113: ...3p E16 PISMO_AUX12 B6 IO DIFFIO_RX104p AG1 PISMO_AUX2 B6 IO DIFFIO_TX103n AA9 PISMO_AUX3 B6 IO DIFFIO_TX103p AA8 PISMO_AUX4 B6 IO DIFFIO_RX103n AD4 PISMO_AUX5 B6 IO DIFFIO_RX103p AD3 PISMO_AUX6 B5 IO DIFFIO_TX67p J6 PISMO_AUX7 B5 IO DIFFIO_RX67n G6 PISMO_AUX8 B5 IO DIFFIO_RX67p G5 PISMO_AUX9 B4 IO DQ0T B4 PISMO_DM_DA0 B4 IO DQ0T D5 PISMO_DM_DA1 B4 IO DQ0T E5 PISMO_DM_DA2 B4 IO DQ0T A4 PISMO_DM_DA3...

Page 114: ...O_DM_DD0 B4 IO DQ6T G10 PISMO_DM_DD1 B4 IO DQ6T G11 PISMO_DM_DD2 B4 IO DQ6T G12 PISMO_DM_DD3 B4 IO DQS7T C12 PISMO_DM_DD4 B4 IO DQ7T D12 PISMO_DM_DD5 B4 IO DQ7T A11 PISMO_DM_DD6 B4 IO DQ7T B11 PISMO_DM_DD7 B4 IO DQS0T C4 PISMO_DM_DQSA_ DH B4 IO DQSn0T C5 PISMO_DM_DQSA_ DL B4 IO DQS2T D7 PISMO_DM_DQSB_ DH B4 IO DQSn2T C7 PISMO_DM_DQSB_ DL B4 IO DQS4T F9 PISMO_DM_DQSC_ DH B4 IO DQSn4T E9 PISMO_DM_DQ...

Page 115: ... PISMO_DM24 B4 IO DQ7T A12 PISMO_DM25 B4 IO G14 PISMO_DM26 B4 IO DQS8T F14 PISMO_DM27 B4 IO DQ8T E13 PISMO_DM28 B4 IO DQ8T F13 PISMO_DM29 B4 IO RDN4 K11 PISMO_DM3 B4 IO DQ8T G13 PISMO_DM30 B4 IO DQSn8T E14 PISMO_DM31 B4 IO DQ8T F15 PISMO_DM32 B4 IO H14 PISMO_DM33 B4 IO L17 PISMO_DM34 B4 IO DQS9T C13 PISMO_DM35 B4 IO DQ9T B14 PISMO_DM36 B4 IO H11 PISMO_DM4 B4 IO K12 PISMO_DM5 B4 IO L13 PISMO_DM6 B4...

Page 116: ...RX107n AE6 PISMO_NA16 B6 IO DIFFIO_RX107p AE5 PISMO_NA17 B6 IO DIFFIO_TX106n AB8 PISMO_NA18 B6 IO DIFFIO_TX106p AB7 PISMO_NA19 B6 IO DIFFIO_TX110n AD7 PISMO_NA2 B6 IO DIFFIO_RX106n AH2 PISMO_NA20 B6 IO DIFFIO_RX106p AH1 PISMO_NA21 B6 IO DIFFIO_TX105n AB10 PISMO_NA22 B6 IO DIFFIO_TX105p AB9 PISMO_NA23 B6 IO DIFFIO_RX105n AF4 PISMO_NA24 B6 IO DIFFIO_RX105p AF3 PISMO_NA25 B6 IO DIFFIO_TX104n AB6 PISM...

Page 117: ...PISMO_SM22 B5 IO DIFFIO_TX83p P10 PISMO_SM23 B5 IO DIFFIO_RX83n M4 PISMO_SM24 B5 IO DIFFIO_RX83p M3 PISMO_SM25 B5 IO DIFFIO_TX82n P5 PISMO_SM26 B5 IO DIFFIO_TX82p P4 PISMO_SM27 B5 IO DIFFIO_RX82n N5 PISMO_SM28 B5 IO DIFFIO_RX82p N4 PISMO_SM29 B5 IO DIFFIO_TX88p T10 PISMO_SM3 B5 IO DIFFIO_TX81n P7 PISMO_SM30 B5 IO DIFFIO_TX81p P6 PISMO_SM31 B5 IO DIFFIO_RX81n L4 PISMO_SM32 B5 IO DIFFIO_RX81p L3 PIS...

Page 118: ...M55 B5 IO DIFFIO_RX75n G2 PISMO_SM56 B5 IO DIFFIO_RX75p G1 PISMO_SM57 B5 IO DIFFIO_TX74n L6 PISMO_SM58 B5 IO DIFFIO_TX74p L5 PISMO_SM59 B5 IO DIFFIO_TX87n T6 PISMO_SM6 B5 IO DIFFIO_RX74n G4 PISMO_SM60 B5 IO DIFFIO_RX74p G3 PISMO_SM61 B5 IO DIFFIO_TX73n M9 PISMO_SM62 B5 IO DIFFIO_TX73p M8 PISMO_SM63 B5 IO DIFFIO_RX73n F2 PISMO_SM64 B5 IO DIFFIO_RX73p F1 PISMO_SM65 B5 IO DIFFIO_TX72n L10 PISMO_SM66 ...

Page 119: ...J7 PISMO_SM86 B5 FPLL10CLKn INPUT D4 PISMO_SM87 B5 FPLL10CLKp INPUT D3 PISMO_SM88 B5 IO DIFFIO_RX87p R2 PISMO_SM9 B7 PLL_ENA PLL_ENA AF8 PLL_ENA B7 PORSEL PORSEL AL2 PORSEL B8 TCK TCK AF24 S2_TCK B8 TDI TDI AL31 S2_TDI B4 TDO TDO C3 S2_TDO B8 TMS TMS AE24 S2_TMS B7 IO AB16 SODIMM_C0 B7 IO AC16 SODIMM_C1 B7 IO AE14 SODIMM_C10 B7 IO DQ8B AG15 SODIMM_C11 B7 IO DQSn8B AH14 SODIMM_C12 B7 IO DQ8B AF13 S...

Page 120: ... DQS3B AL7 SODIMM_C34 B7 IO AB13 SODIMM_C35 B7 IO AD12 SODIMM_C36 B7 IO DQSn2B AL6 SODIMM_C37 B7 IO AE11 SODIMM_C38 B7 IO DQ1B AH9 SODIMM_C39 B7 IO DQSn9B AL13 SODIMM_C4 B7 IO DQS1B AG8 SODIMM_C40 B7 IO AD11 SODIMM_C41 B7 IO AC12 SODIMM_C42 B7 IO DQSn0B AK5 SODIMM_C43 B7 IO AC11 SODIMM_C44 B7 IO AB12 SODIMM_C45 B7 IO AE10 SODIMM_C46 B7 IO RDN7 AB11 SODIMM_C47 B7 IO RUP7 AD10 SODIMM_C48 B7 IO AE9 S...

Page 121: ...B AK7 SODIMM_D18 B7 IO DQ3B AM7 SODIMM_D19 B7 IO DQ7B AJ12 SODIMM_D2 B7 IO DQ2B AM6 SODIMM_D20 B7 IO DQ2B AJ6 SODIMM_D21 B7 IO DQ2B AK6 SODIMM_D22 B7 IO DQ2B AM5 SODIMM_D23 B7 IO DQSn1B AH8 SODIMM_D24 B7 IO DQ1B AH7 SODIMM_D25 B7 IO DQ1B AH6 SODIMM_D26 B7 IO DQ1B AG9 SODIMM_D27 B7 IO DQ0B AM4 SODIMM_D28 B7 IO DQ0B AH5 SODIMM_D29 B7 IO DQ7B AK12 SODIMM_D3 B7 IO DQ0B AJ5 SODIMM_D30 B7 IO DQ0B AL4 SO...

Page 122: ...O_RX102p AF1 SODIMM_S3 B6 IO DIFFIO_TX101n Y11 SODIMM_S4 B6 IO DIFFIO_TX101p Y10 SODIMM_S5 B6 IO DIFFIO_RX101n AE4 SODIMM_S6 B6 IO DIFFIO_RX101p AE3 SODIMM_S7 B6 IO DIFFIO_TX100n AA7 SODIMM_S8 B6 IO DIFFIO_TX100p AA6 SODIMM_S9 B8 TRST TRST AK30 TRST B8 IO CS AC22 UGRID0 B8 IO CLKUSR AD23 UGRID1 B12 IO PLL12_OUT1n AH18 UGRID10 B12 IO PLL12_OUT1p AJ18 UGRID11 B12 IO PLL12_OUT0n AK18 UGRID12 B12 IO P...

Page 123: ...B1 UGRID34 B6 IO DIFFIO_TX94n W9 UGRID35 B6 IO DIFFIO_TX94p W8 UGRID36 B6 IO DIFFIO_RX94n Y5 UGRID37 B6 IO DIFFIO_RX94p Y4 UGRID38 B6 IO DIFFIO_TX93n V5 UGRID39 B8 IO RUnLU AG17 UGRID4 B6 IO DIFFIO_TX93p V4 UGRID40 B6 IO DIFFIO_RX93n AA4 UGRID41 B6 IO DIFFIO_RX93p AA3 UGRID42 B6 IO DIFFIO_TX92n V7 UGRID43 B6 IO DIFFIO_TX92p V6 UGRID44 B6 IO DIFFIO_RX92n AA2 UGRID45 B6 IO DIFFIO_RX92p AA1 UGRID46 B...

Page 124: ...OUT1n D16 UGRID67 B9 IO PLL5_OUT1p C16 UGRID68 B11 IO PLL11_OUT0p B18 UGRID69 B8 IO nCS AG18 UGRID7 B11 IO PLL11_OUT0n C18 UGRID70 B11 IO PLL11_OUT1p D18 UGRID71 B11 IO PLL11_OUT1n E18 UGRID72 B11 IO PLL11_FBp OUT2p A19 UGRID73 B11 IO PLL11_FBn OUT2n B19 UGRID74 B3 IO INIT_DONE G25 UGRID75 B12 IO PLL12_FBn OUT2n AL19 UGRID8 B12 IO PLL12_FBp OUT2p AM19 UGRID9 B11 VCC_PLL11_OUT J17 VCC_PLL11 B12 VCC...

Page 125: ...H7 VCCD_PLL VCCD_PLL11 J18 VCCD_PLL VCCD_PLL4 T9 VCCD_PLL VCCD_PLL1 U24 VCCD_PLL VCCD_PLL3 U7 VCCD_PLL VCCD_PLL2 V25 VCCD_PLL VCCIO1 AA28 VCCIO_1 VCCIO1 AK32 VCCIO_1 VCCIO1 U21 VCCIO_1 VCCIO1 V32 VCCIO_1 VCCIO2 C32 VCCIO_2 VCCIO2 M28 VCCIO_2 VCCIO2 R32 VCCIO_2 VCCIO2 T21 VCCIO_2 VCCIO3 A18 VCCIO_3 VCCIO3 A30 VCCIO_3 VCCIO3 E21 VCCIO_3 VCCIO3 M17 VCCIO_3 VCCIO4 A15 VCCIO_4 VCCIO4 A3 VCCIO_4 VCCIO4 ...

Page 126: ...VREFB1 B2 VREFB2N0 VREFB2N0 F28 VREFB2 B2 VREFB2N1 VREFB2N1 J28 VREFB2 B2 VREFB2N2 VREFB2N2 P30 VREFB2 B3 VREFB3N0 VREFB3N0 C19 VREFB3 B3 VREFB3N2 VREFB3N2 C31 VREFB3 B3 VREFB3N1 VREFB3N1 D24 VREFB3 B4 VREFB4N2 VREFB4N2 C14 VREFB4 B4 VREFB4N0 VREFB4N0 C2 VREFB4 B4 VREFB4N1 VREFB4N1 D9 VREFB4 B5 VREFB5N2 VREFB5N2 F5 VREFB5 B5 VREFB5N1 VREFB5N1 J5 VREFB5 B5 VREFB5N0 VREFB5N0 P3 VREFB5 B6 VREFB6N1 VR...

Page 127: ... VREFB7N2 AK2 VREFB7 B8 VREFB8N1 VREFB8N1 AJ24 VREFB8 B8 VREFB8N2 VREFB8N2 AK19 VREFB8 B8 VREFB8N0 VREFB8N0 AK31 VREFB8 B5 CLK11p INPUT T3 XTAL_CLK Table 7 6 FPGA Pins Sorted by Signal Name Continued Bank Pin Type Name Other Pin Information Configuration Function Ball Board Net ...

Page 128: ...7 82 AT91CAP9A DK Development Kit User Guide 6321B CAP 02 Jul 07 ...

Page 129: ...ge selection RR1 RR7 EBI shunts some are on the opposite side J17 BMS jumper boot mode selection J12 VDDIOM current measurement jumper Upper pin CAP chip VDDIOM inputs Lower pin board regulated VDDIOM voltage J14 VDDBU current measurement jumper Left pin CAP chip VDDBU inputs Right pin board regulated voltage J22 8 7 6 9 23 current measurement jumpers see doc Input voltages are Upper pins board re...

Page 130: ...ction See schematics Section 16 1 TP1 Testpoint for DM_VREF injection if needed J22 ON CAP VDDCORE circuit opener current measurement purpose J8 ON CAP VDDIOP0 circuit opener current measurement purpose J9 ON CAP VDDUTMI12 circuit opener current measurement purpose J12 ON CAP VDDIOM circuit opener current measurement purpose J14 ON CAP VDDBU circuit opener current measurement purpose J15 ON CAP VD...

Page 131: ...ointly to develop AT91CAP9 processor applications Section 9 through Section 11 provide essential usage documentation for the AT91CAP 1 8V Memory Extension Board AT91CAP MEM18 Figure 9 1 AT91CAP MEM18 Overview 9 2 Purpose The AT91CAP MEM18 board provides a composite memory extension for any AT91CAP9 DK mezza nine Its featured devices are 1 8V powered Memory Extension CAP Mezzanine Motherboard ...

Page 132: ...9 2 AT91CAP9A DK Development Kit User Guide 6321B CAP 02 Jul 07 ...

Page 133: ...metallic element 10 2 Requirements In order to set up an AT91CAP9A DK development system the following items are needed AT91CAP9A DKZ mezzanine board Memory extension board such as the AT91CAP MEM18 AT91CAP DKM motherboard PC ATX standard power supply unit 10 3 Layout The board features a set of memory devices connected together on the same address data bus Burst cellular RAM NAND Flash Mobile DDR...

Page 134: ...0 4 Powering Up the Board The AT91CAP MEM18 memory extension is powered by the AT91CAP9A DKZ mezzanine it is con nected to This is automatically configured via resistor R6 This resistor sets the output level of an adjustable voltage regulator located on the mezzanine ...

Page 135: ...EM18 Configuration Items Designation Default Setting Feature J2 ON NAND Flash chip select circuit opener Removing the jumper disables the access to the NAND Flash device This may be useful in case of corrupted contents in order to force the system to boot on another default device refer to AT91CAP9 chip and mezzanine documentation in this case ...

Page 136: ...11 2 AT91CAP9A DK Development Kit User Guide 6321B CAP 02 Jul 07 ...

Page 137: ...ointly to develop AT91CAP9 processor applications Section 12 through Section 14 provide essential usage documentation for the AT91CAP 3 3V Memory Extension Board AT91CAP MEM33 Figure 12 1 AT91CAP MEM33 Overview 12 2 Purpose The AT91CAP MEM33 board provides a composite memory extension for any AT91CAP9 DK mezza nine Its featured devices are 3 3V powered Memory Extension CAP Mezzanine Motherboard ...

Page 138: ...12 2 AT91CAP9A DK Development Kit User Guide 6321B CAP 02 Jul 07 ...

Page 139: ...tive device should be worn when handling the board Avoid touching the component pins or any other on board metallic element 13 2 Requirements In order to set up an AT91CAP9A DK development system the following items are needed AT91CAP9A DKZ mezzanine board Memory extension board such as the AT91CAP MEM33 AT91CAP DKM motherboard PC ATX standard power supply unit 13 3 Layout The board features a set...

Page 140: ...d by the AT91CAP9A DKZ mezzanine it is con nected to This is automatically configured via resistor R6 This resistor sets the output level of an adjustable voltage regulator located on the mezzanine MN3b NAND FLASH D0 D7 MN1 SDRAM D0 15 MN4 serial EEPROM TWI bus optional MN3a NAND FLASH D0 D15 J2 NAND FLASH Chip Select enabler TOP SIDE MN2 SDRAM D16 31 MN5 NOR FLASH D0 15 BOTTOM SIDE ...

Page 141: ...MEM18 Configuration Items Designation Default Setting Feature J2 ON NOR Flash chip select circuit opener Removing the jumper disables the access to the NOR Flash device This may be useful in case of corrupted contents in order to force the system to boot on another default device refer to AT91CAP9 chip and mezzanine documentation in this case ...

Page 142: ...14 2 AT91CAP9A DK Development Kit User Guide 6321B CAP 02 Jul 07 ...

Page 143: ...ics AT91CAP9 DKM Diagram Power Supply Mezzanine Connectors FPGA Connectors Upstream Interfaces User Interface and PIOs Ethernet RJ45 Connector Serial Interfaces Serial Debug Port CAN Bus USB Host Interface Serial Devices Image Sensor Connector SD Card MMC Card DataFlash Card Interface SD Card MMC Card Interface Serial EEPROM Audio AC97 ADC Inputs Audio I2S LCD Panel ...

Page 144: ...tion shall expose offender to legal proceedings INIT EDIT A AT91CAP DKM 1 13 27 OCT 06 B JPG DIAGRAM XX XXX XX XXX JPG 24 APR 07 B REV DATE MODIF DES DATE VER SCALE 1 1 REV SHEET This agreement is our property Reproduction and publication without our written authorization shall expose offender to legal proceedings INIT EDIT A AT91CAP DKM 1 13 27 OCT 06 B JPG DIAGRAM XX XXX XX XXX JPG 24 APR 07 B R...

Page 145: ...PLY 5V STDBY C11 15PF C11 15PF Q1 BSH103 Q1 BSH103 1 3 2 L1 2 2µH L1 2 2µH C7 10µF C7 10µF J5 J5 C12 10µF C12 10µF C10 10µF C10 10µF R2 10K R2 10K C120 10µF C120 10µF MN1 LTC1765 MN1 LTC1765 GND1 1 BOOST 2 SYNC 14 SHDN 11 VIN1 3 GND2 8 GND4 9 GND5 16 VIN2 4 SW2 5 SW1 6 NC1 7 NC3 15 VC 13 FB 12 NC2 10 GND3 17 R8 10K R8 10K C9 180NF C9 180NF CR3 BAT20J CR3 BAT20J 2 1 CR1 BAT20J CR1 BAT20J 2 1 CR6 ST...

Page 146: ... CONNECTORS XX XXX XX XXX JPG 24 APR 07 B REV DATE MODIF DES DATE VER SCALE 1 1 REV SHEET This agreement is our property Reproduction and publication without our written authorization shall expose offender to legal proceedings INIT EDIT A AT91CAP DKM 3 13 27 OCT 06 B JPG MEZZANINE CONNECTORS XX XXX XX XXX JPG 24 APR 07 B REV DATE MODIF DES DATE VER SCALE 1 1 REV SHEET This agreement is our propert...

Page 147: ...ction and publication without our written authorization shall expose offender to legal proceedings INIT EDIT A AT91CAP DKM 4 13 27 OCT 06 B JPG FPGA CONNECTORS XX XXX XX XXX JPG 24 APR 07 B REV DATE MODIF DES DATE VER SCALE 1 1 REV SHEET This agreement is our property Reproduction and publication without our written authorization shall expose offender to legal proceedings INIT EDIT A AT91CAP DKM 4...

Page 148: ...NTERFACE FPGA BANK3 Powered by VCCIO3 R30 0R R30 0R R20 0R R20 0R R29 0R R29 0R J15 J15 1 2 3 R32 22K R32 22K C18 100NF C18 100NF J16 AMP 292304 1 J16 AMP 292304 1 1 4 2 3 5 6 R31 15K R31 15K C15 100NF C15 100NF MN5 ISP1105BS MN5 ISP1105BS OE 1 RCV 2 VP 3 VM 4 SUSPND 5 MODE 6 VCCIO 7 SPEED 8 D 9 D 10 VPO VO 11 VMO FSE0 12 Vreg33 13 VCC5 14 Vpu 15 SOFTCON 16 GNDPAD 17 C17 100NF C17 100NF R34 33R 1 ...

Page 149: ...fender to legal proceedings INIT EDIT A AT91CAP DKM 6 13 27 OCT 06 B JPG USER INTERFACE PIO XX XXX XX XXX JPG 24 APR 07 B REV DATE MODIF DES DATE VER SCALE 1 1 REV SHEET This agreement is our property Reproduction and publication without our written authorization shall expose offender to legal proceedings INIT EDIT A AT91CAP DKM 6 13 27 OCT 06 B JPG USER INTERFACE PIO XX XXX XX XXX JPG 24 APR 07 B...

Page 150: ... TD CT NC RD CT TX TX RX RX RD J21 J00 0061NL PULSE 1 2 7 8 3 6 5 4 15 16 R66 10K R66 10K C33 100NF C33 100NF C24 100NF C24 100NF DS4 YELLOW DS4 YELLOW 2 1 C29 10V 10µF C29 10V 10µF R54 0R R54 0R C23 100NF C23 100NF R60 10K R60 10K R68 1K R68 1K C31 100NF C31 100NF R47 0R R47 0R C25 100NF C25 100NF R53 49R9 1 R53 49R9 1 R55 0R R55 0R L4 742792093 L4 742792093 C34 100NF C34 100NF DS5 GREEN DS5 GREE...

Page 151: ...N BUS NOT POPULATED NOT POPULATED USB HOST INTERFACE R75 0R R75 0R C48 47pF C48 47pF F2 500 mA F2 500 mA R89 39R R89 39R C46 47pF C46 47pF R91 15K R91 15K R74 100K R74 100K R90 39R R90 39R C39 100NF C39 100NF J25 J25 C41 10V 10µF C41 10V 10µF J23 MALE RIGHT ANGLE FCI D09P13A4GX00LF J23 MALE RIGHT ANGLE FCI D09P13A4GX00LF 5 4 3 2 1 9 8 7 6 10 11 Rs D EN R CANH CANL VCC GND MN9 SN65HVD234 Rs D EN R ...

Page 152: ...TE MODIF DES DATE VER SCALE 1 1 REV SHEET This agreement is our property Reproduction and publication without our written authorization shall expose offender to legal proceedings INIT EDIT A AT91CAP DKM 9 13 27 OCT 06 B JPG SERIAL DEVICES XX XXX XX XXX JPG 24 APR 07 B IMAGE SENSOR CONNECTOR SD CARD MMC CARD INTERFACE SD CARD MMC CARD DATAFLASH CARD INTERFACE SERIAL EEPROM R100 2 2K R100 2 2K C51 1...

Page 153: ...MHz Y2 24 576MHz R120 3 9K R120 3 9K C55 6V3 100µF C55 6V3 100µF C69 270 pF C69 270 pF C75 1µF C75 1µF L11 742792093 L11 742792093 R112 2 2K R112 2 2K R104 NOT POPULATED R104 NOT POPULATED R108 NOT POPULATED R108 NOT POPULATED C79 100NF C79 100NF R109 47R R109 47R C58 100NF C58 100NF R106 1K R106 1K C73 100NF C73 100NF C62 22PF C62 22PF R125 NOT POPULATED R125 NOT POPULATED R113 4 7K R113 4 7K C86...

Page 154: ...DKM 11 13 27 OCT 06 B JPG ADC INPUTS XX XXX XX XXX JPG 24 APR 07 B REV DATE MODIF DES DATE VER SCALE 1 1 REV SHEET This agreement is our property Reproduction and publication without our written authorization shall expose offender to legal proceedings INIT EDIT A AT91CAP DKM 11 13 27 OCT 06 B JPG ADC INPUTS XX XXX XX XXX JPG 24 APR 07 B R133 1K R133 1K R132 R132 J33 PHOENIX CONTACT MKDS 1 6 3 81 J...

Page 155: ... 3 VINR1 4 VADCN 5 VINL2 6 VADCP 7 IPSEL 9 VDDD 10 VINR2 8 VSSD 11 SYSCLK 12 VDDADAC 25 QMUTE 23 STATUS 22 STATIC 21 TEST1 20 DATAI 19 DATAO 18 WS 17 BCK 16 L3DATA 15 L3CLOCK 14 L3MODE 13 VOUTR 24 VSSADAC 27 VOUTL 26 VREF 28 R142 100R R142 100R R141 0R R141 0R J35 3 5 PHONEJACK STEREO J35 3 5 PHONEJACK STEREO 2 1 4 3 5 R1561R R1561R R149 10K R149 10K RR2 100K RR2 100K 1 5 2 3 4 6 7 8 C99 100NF C99...

Page 156: ...CREEN CONTROLLER LCDD12 LCDD5 LCDD15 LCDD6 LCDD3 LCDD4 LCDHSYNC LCDD2 LCDD20 LCDD23 LCDD21 LCDDDOTCK LCDDEN LCDD13 LCDD22 LCDD18 LCDD14 LCDD11 LCDD10 LCDD19 LCDD7 3 5 inch 1 4 VGA TFT LCD DISPLAY C119 100NF C119 100NF R159 NOT POPULATED R159 NOT POPULATED TP4 TP4 R164 0R R164 0R MN15 ADS7843E MN15 ADS7843E XP 2 IN3 7 YP 3 XM 4 YM 5 GND 6 IN4 8 VREF 9 VCC 10 VCC 1 DCLK 16 CS 15 DIN 14 BUSY 13 DOUT ...

Page 157: ...15 2 AT91CAP9A DK Development Kit User Guide 6321B CAP 02 Jul 07 ...

Page 158: ...ppended schematics AT91CAP9A DKZ Mezzanine Board Top Level FPGA User I O Through hole Grid Motherboard Connectors FPGA PISMO Connectors CAP Power Supply CAP Busses CAP USB PLL ICE CAP SODIMM EBI FPGA Power 1 2 FPGA Power 2 2 FPGA I Os FPGA I Os Configuration Banks 1 6 FPGA I Os Configuration Banks 7 8 FPGA I Os Configuration JTAG AS Mode FPGA SODIMM EBI ...

Page 159: ...NO FIDU FD3 FEED NO FIDU FD3 FEED NO FIDU CONFIG 13_CONFIG VCCIO_8 S2_TCK S2_TMS S2_TDO S2_TDI DCLK nCONFIG nCSO DATA0 GND 3V3 nCE CONFIG_DONE ASDO FD4 FEED NO FIDU FD4 FEED NO FIDU FPGA_SODIMM 14_FPGA_SODIMM VCCIO_6 VCCIO_7 SODIMM_C 0 53 GND SODIMM_S 0 18 SODIMM_DQS 0 1 SODIMM_D 0 31 5V FPGA 09_FPGA FPGA 0 275 PISMO_NA 0 26 PISMO_SM 0 88 PISMO_AUX 0 12 SODIMM_S 0 18 PISMO_DM_DQSA_DH PISMO_DM_DQSA...

Page 160: ...CALE 1 1 REV SHEET This agreement is our property Reproduction and publication without our written authorization shall expose offender to legal proceedings INIT EDIT A AT91CAP9A DKZ 2 14 XX SEP 06 B XX XXX 06 YRDE XXX MEZZANINE BOARD B 04 MAY 07 YRDE REV DATE MODIF DES DATE VER SCALE 1 1 REV SHEET This agreement is our property Reproduction and publication without our written authorization shall e...

Page 161: ...EET This agreement is our property Reproduction and publication without our written authorization shall expose offender to legal proceedings INIT EDIT A AT91CAP9A DKZ 3 14 XX SEP 06 B XX XXX 06 YRDE XXX MEZZANINE BOARD B 04 MAY 07 YRDE REV DATE MODIF DES DATE VER SCALE 1 1 REV SHEET This agreement is our property Reproduction and publication without our written authorization shall expose offender ...

Page 162: ...O_4 DM_VCC DM_VCC DM_VCC DM_VCC PISMO_DM25 PISMO_DM23 VCCIO_6 VCCIO_6 VCCIO_4 PISMO_AUX1 PISMO_SM88 PISMO_SM87 DM_VREF PISMO_FS5 PISMO_AUX5 DM_VCC 3V3 1V8 2V5 GND VCCIO_4 VCCIO_5 VCCIO_6 PISMO_NA 0 26 PISMO_FS 0 9 PISMO_DM_DA 0 7 PISMO_DM_DB 0 7 PISMO_SM 0 88 PISMO_DM_DC 0 7 PISMO_AUX 0 12 PISMO_DM_DD 0 7 PISMO_DM 0 36 PISMO_DM_DQSB_DL PISMO_DM_DQSB_DH PISMO_DM_DQSD_DH PISMO_DM_DQSD_DL PISMO_DM_DQ...

Page 163: ...DCORE H7 VDDCORE R5 VDDCORE T4 PLLBVDD33 E17 PLL480_VDD C18 UTMI_VDD33 B19 VDDIOP0 B17 VDDIOP0 A15 VDDIOP0 E11 VDDIOP0 G9 VDDIOP0 F7 VDDIOP0 J6 VDDIOP1 H6 UTMI_VDD C19 VDDIOM V5 VDDIOM R8 VDDIOM R13 VDDIOM R11 VDDIOM F6 VDDIOM N8 VDDIOM P6 VDDMPIOA Y14 VDDMPIOA U16 VDDMPIOB V20 VDDMPIOB P20 VDDMPIOB H12 VDDBU E18 VDDADC C11 PLLAVDD33 G17 VREFP B12 C10 100nF C10 100nF C3 100nF C3 100nF C46 100nF C4...

Page 164: ...ISI_D8 M8 PA29 TIOA0 ISI_D9 L3 PA30 TIOB0 ISI_D10 M2 PA31 DMARQ1 ISI_D11 L4 R80 1K R80 1K CAP9 EBI AT91CAP9 U2C CAP9 EBI AT91CAP9 U2C BCCLK U3 CAS BCOE R4 DQS0 T6 DQS1 U8 NANDOE D7 NANDWE W3 NCS0 Y11 NCS1 BCCS N9 NRD CFOE M13 NWR0 NWE CFWE W11 NWR1 NBS1 CFIOR U7 NWR3 NBS3 CFIOW P7 OWAIT W2 RAS BCADV V2 SDA10 T10 SDCKE BCCRE V3 SDCK Y1 SDCKN Y2 SDDRCS T5 SDWE BCWE W1 D0 U5 D1 U6 D10 P9 D11 T8 D12 R...

Page 165: ..._FSDM A18 UTMI_FSDP A17 USBHA_DM B16 USBHB_DM D17 USBHA_DP C16 USBHB_DP C17 NC12 F14 NC11 F15 NC9 G16 NC10 H16 HSDM A20 HSDP A19 BMS A6 JTAGSEL H13 NRST A7 NTRST C9 RTCK E10 SHDW F19 TCK B8 TDI C10 TDO B7 TMS D10 TST G19 WKUP0 F18 R12 0R FEED NO R12 0R FEED NO USB MINIB J16 MOLEX_0548190572 USB MINIB J16 MOLEX_0548190572 VBUS 1 DM 2 DP 3 ID 4 GND 5 SH1 6 SH2 7 R33 6 8k R33 6 8k R18 39R R18 39R TP3...

Page 166: ...roduction and publication without our written authorization shall expose offender to legal proceedings INIT EDIT A AT91CAP9A DKZ 8 14 XX SEP 06 B XX XXX 06 YRDE XXX MEZZANINE BOARD B 04 MAY 07 YRDE REV DATE MODIF DES DATE VER SCALE 1 1 REV SHEET This agreement is our property Reproduction and publication without our written authorization shall expose offender to legal proceedings INIT EDIT A AT91C...

Page 167: ...F C96 100nF C110 100nF C110 100nF C91 100nF C91 100nF C86 100nF C86 100nF C71 100nF C71 100nF C105 100nF C105 100nF C100 100nF C100 100nF C80 100nF C80 100nF C75 100nF C75 100nF C63 100nF C63 100nF C65 100nF C65 100nF C97 100nF C97 100nF C92 100nF C92 100nF C106 100nF C106 100nF C87 100nF C87 100nF C101 100nF C101 100nF C68 100nF C68 100nF C81 100nF C81 100nF C76 100nF C76 100nF U7K ALTERA EP2S90F...

Page 168: ...O R51 0R FEED NO L4 4 7uH 220mA L4 4 7uH 220mA C124 100nF C124 100nF C119 100nF C119 100nF C148 2 2uF C148 2 2uF C204 1000uF C204 1000uF C132 100nF C132 100nF C179 100nF C179 100nF C215 47uF C215 47uF R36 0R CPN AT91RES014 R36 0R CPN AT91RES014 C135 100nF C135 100nF C173 100nF C173 100nF C118 100nF C118 100nF L5 4 7uH L5 4 7uH C115 100nF C115 100nF C170 10nF C170 10nF L6 4 7uH 220mA L6 4 7uH 220mA...

Page 169: ...N2_V7 V7 IO_VB6N0_AG3 AG3 IO_VB6N0_AG4 AG4 IO_VB6N1_AF1 AF1 IO_VB6N1_AF2 AF2 IO_VB6N1_AF3 AF3 IO_VB6N1_AF4 AF4 IO_VB6N1_AG1 AG1 IO_VB6N1_AG2 AG2 IO_VB6N0_AH3 AH3 IO_VB6N0_AH4 AH4 IO_VB6N0_AJ1 AJ1 IO_VB6N0_AJ2 AJ2 IO_VB6N1_AH1 AH1 IO_VB6N1_AH2 AH2 U7A ALTERA EP2S90F1020 Version 1 0 U7A ALTERA EP2S90F1020 Version 1 0 IO_VB1N0_AA26 AA26 IO_VB1N0_AA27 AA27 IO_VB1N0_AA29 AA29 IO_VB1N0_AA30 AA30 IO_VB1N...

Page 170: ..._VB7N1_AL7 AL7 IO_VB7N1_AL8 AL8 IO_VB7N1_AL9 AL9 IO_VB7N1_AM10 AM10 IO_VB7N1_AM11 AM11 IO_VB7N1_AM7 AM7 IO_VB7N1_AM8 AM8 IO_VB7N1_AM9 AM9 IO_VB7N2_AJ6 AJ6 IO_VB7N2_AK4 AK4 IO_VB7N2_AK5 AK5 IO_VB7N2_AK6 AK6 IO_VB7N2_AL4 AL4 IO_VB7N2_AL5 AL5 IO_VB7N2_AL6 AL6 IO_VB7N2_AM4 AM4 IO_VB7N2_AM5 AM5 IO_VB7N2_AM6 AM6 RDN7 AB11 RUP7 AD10 IO_VB7N1_AJ7 AJ7 IO_VB7N1_AJ8 AJ8 IO_VB7N1_AJ10 AJ10 IO_VB7N1_AJ11 AJ11 ...

Page 171: ...14 XX SEP 06 B XX XXX 06 YRDE XXX MEZZANINE BOARD B 04 MAY 07 YRDE REV DATE MODIF DES DATE VER SCALE 1 1 REV SHEET This agreement is our property Reproduction and publication without our written authorization shall expose offender to legal proceedings INIT EDIT A AT91CAP9A DKZ 13 14 XX SEP 06 B XX XXX 06 YRDE XXX MEZZANINE BOARD B 04 MAY 07 YRDE JTAG AS Mode FPGA I Os config R69 0R R69 0R J21 HTST...

Page 172: ... SCALE 1 1 REV SHEET This agreement is our property Reproduction and publication without our written authorization shall expose offender to legal proceedings INIT EDIT A AT91CAP9A DKZ 14 14 XX SEP 06 B XX XXX 06 YRDE XXX MEZZANINE BOARD B 04 MAY 07 YRDE REV DATE MODIF DES DATE VER SCALE 1 1 REV SHEET This agreement is our property Reproduction and publication without our written authorization shal...

Page 173: ...16 2 AT91CAP9A DK Development Kit User Guide 6321B CAP 02 Jul 07 ...

Page 174: ...AT91CAP9A DK Development Kit User Guide 17 1 6321B CAP 02 Jul 07 Section 17 AT91CAP MEM18 Schematics 17 1 Schematics This section contains the following appended schematics AT91CAP MEM18 ...

Page 175: ...G4 VSS H6 ALE A2 N C C4 N C C3 N C C5 N C C6 CLE B3 N C D6 N C G1 I O1 G2 I O3 H3 I O2 H2 N C E3 N C E4 N C E5 I O7 G6 I O6 H5 I O5 G5 I O4 H4 N C E6 N C E2 VSS A3 N C F3 C18 10V 10µF C18 10V 10µF R6 4 87K R6 4 87K C2 100NF C2 100NF J2 J2 1 2 MN4 AT24C512N MN4 AT24C512N A0 1 A1 2 WP 7 SCL 6 VCC 8 NC 3 SDA 5 GND 4 MN2 MT45W8MW16BGX MN2 MT45W8MW16BGX A0 A3 A1 A4 A2 A5 A3 B3 A4 B4 A5 C3 A6 C4 A7 D4 A...

Page 176: ...AT91CAP9A DK Development Kit User Guide 18 1 6321B CAP 02 Jul 07 Section 18 AT91CAP MEM33 Schematics 18 1 Schematics This section contains the following appended schematics AT91CAP MEM33 ...

Page 177: ...0 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 5 C15 100NF C15 100NF R6 0R R6 0R R12 0R R12 0R R5 NOT POPULATED R5 NOT POPULATED C7 100NF C7 100NF C20 10V 10µF C20 10V 10µF C6 100NF C6 100NF C9 100NF C9 100NF C2 100NF C2 100NF C5 100NF C5 100NF R9 10K R9 10K R13 0R R13 0R C19 100NF C19 100NF C1 100NF C1 100NF C8 100NF C8 100NF C10 100NF C1...

Page 178: ...CAP9A DK Development Kit User Guide 19 1 6321B CAP 02 Jul 07 Section 19 Errata 19 1 Known Errata There are presently no known errata on any of the boards associated with the AT91CAP9A DK develop ment system ...

Page 179: ...Pin Assignment Table Table 3 3 J10 female Pin Assignment Table Table 3 4 PCI64 Extension Connector Table Section 3 14 4 USB Device interfaces Warning updated and update to Table 3 5 USB Interface and FPGA Connection 4509 Section 7 7 6 FPGA Pinout Tables Updates to Table 7 5 FPGA Pins Sorted by Bank Signal Name and Table 7 6 FPGA Pins Sorted by Signal Name Section 15 AT91CAP DKM Schematics updated ...

Page 180: ...IED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT INDIRECT CONSEQUENTIAL PUNITIVE SPECIAL OR INCIDEN TAL DAMAGES INCLUDING WITHOUT LIMITATION DAMAGES FOR LOSS OF PROFITS BUSINESS INTERRUPTION OR LOSS OF INFORMATION ARISING OUT O...

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