Atmel AT91CAP9, User Manual

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AT91CAP9A-DK Development Kit User Guide 7-21
6321B–CAP–02-Jul-07
7.7.5 User LEDs and I/O Grid
The 1.27 mm spaced I/O grid gathers miscellaneous yet unused FPGA signals. The user must be aware
that some of these signals share configuration functions and therefore may be active at boot time.
Note also the four signals that drive the user LEDs
„ UGRID55 (LED DS2 - left)
„ UGRID56 (LED DS3)
„ UGRID57 (LED DS4)
„ UGRID58 (LED DS5 - right)
The grid matrix assignment is as follows:
„ Column A = UGRID00.. 09 (A0 = UGRID00.. A9 = UGRID09)
„ Column B = UGRID10..19
„ Column C = UGRID20..29
„ Column D = UGRID30..39
„ Column E = UGRID40..49
„ Column F = UGRID50..59
„ Column G = UGRID60..69
„ Column H = UGRID70..75, 3.3V, 3.3V, GND, GND
H36 DNU2 n.c.
H37 SM_CS3# PISMO_SM46 M7 DIFFIO_TX77n 5
H38 SM_CS2# PISMO_SM45 J1 DIFFIO_RX78p 5
H39 SM_CS1# PISMO_SM44 J2 DIFFIO_RX78n 5
H40 SM_CS0# PISMO_SM43 N6 DIFFIO_TX78p 5
Table 7-3. PISMO-FPGA Signal Assignment (Continued)
PISMO
Pin Standard PISMO
Name
Board Signal Name FPGA Pin
Alternate FPGA
Pin Function
FPGA Bank
Table 7-4. I/O Grid
FPGA Bank Pin Name Alternate Function Configuration Function Board Signal Name FPGA Bank
B8 IO CS AC22 UGRID00
B8 IO CLKUSR AD23 UGRID01
B8 IO nWS AE23 UGRID02
B8 IO nRS AF23 UGRID03
B8 IO RUnLU AG17 UGRID04
B8 IO DEV_OE AH17 UGRID05
B8 IO DEV_CLRn AG19 UGRID06
B8 IO nCS AG18 UGRID07
B12 IO PLL12_FBn/OUT2n AL19 UGRID08
B12 IO PLL12_FBp/OUT2p AM19 UGRID09
B12 IO PLL12_OUT1n AH18 UGRID10