Atmel AT91CAP9, User Manual

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4-2 AT91CAP9A-DK Development Kit User Guide
6321B–CAP–02-Jul-07
Table 4-1. AT91CAP-DKM Configuration Jumpers and Straps
Designation Default Setting Feature
C45, 46, 47, 48 OFF
Optional 47 pF filtering capacitors for Host USB port lines (see
“AT91CAP-DKM
Schematics”
)
J1 no default
Selects which SSC drives the I2S interface. All jumpers in the upper position will select SSC0,
all jumpers in the lower position will select SSC1.
J11 2-3 Selects FPGA USB interface MN4/J12 bus speed
(1)
J13 2-3 Selects FPGA USB interface MN5/J14 bus speed
(1)
J15 2-3 Selects FPGA USB interface MN6/J16 bus speed
(1)
J2 1-2
Selects the TouchScreen controller selection signal. Default position = 2-3 (NPCS3).
Position 1-2 chooses NPCS2.
J22 ON Enables the Ethernet PHY MN7 auto MDIX control.
J25 ON Applies 120 Ohm termination to the CAN port MN9/J24
J3 no default
These four jumpers select ADC channels (0123 or 4567) to be assigned to the four ADC
inputs.
Upper position selects channels 4567. Lower position selects channels 0123. Each jumper can
be indifferently set to upper or lower position, no matter the position of the others.
See
“AT91CAP-DKM Schematics”
for more details.
J5 OFF
Forces PC/ATX power supply power on. To be installed in case the SHDN signal (normally
provided by the AT91CAP9 chip) is non operating or absent for some reason.
R104, 107
ON, ON
(use 1K Ohm
resistors)
Select the AC97 AD1981B clock frequency. Refer to
“AT91CAP-DKM Schematics”
and/or
the AD1981B datasheet for in-depth explanations.
R123, 125 OFF, OFF
Optional MIC input biasing to VREFOUT for the AC97 AD1981B chip. Refer to
“AT91CAP-
DKM Schematics”
and/or the AD1981B datasheet for in-depth explanations.
R153, 154 OFF, OFF
Optionally connects the I2S input lines to the secondary input channel of the UDA1342TS
MN14 device. Use 0 Ohm resistors if needed.
R159 OFF Reserved for future use. Do not mount.
R169 OFF
Optional divider bridge resistor (to be calculated jointly with R166) in order to adjust the touch
screen controller VREF between 0 and 3.3V.
R171 OFF
Connects the analog 3.3V power line of the ADC input buffers to the dedicated connector J33.
Use a 0 Ohm resistor if needed.
R172, 173, 174
ON, OFF, OFF
(2)
Select FPGA IO BANK 1 VCCO voltage
(3)
R175, 176, 177
ON, OFF, OFF
(2)
Select FPGA IO BANK 2 VCCO voltage
(3)
R178, 179, 180
ON, OFF, OFF
(2)
Select FPGA IO BANK 3 VCCO voltage
(3)
R18, 19 ON, OFF
Selects ISP1105BS PHY MN4 mode input. Please refer to the datasheet of this device for in-
depth details.
R27, 28 ON, OFF
Selects ISP1105BS PHY MN5 mode input. Please refer to the datasheet of this device for in-
depth details.