Atmel AT91CAP9, User Manual

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3-12 AT91CAP9A-DK Development Kit User Guide
6321B–CAP–02-Jul-07
Pins not listed in Table 3-3 below are not connected.
181 B2 IO DIFFIO_TX49n K26 FPGA107
182 GND
183 B2 IO DIFFIO_RX48p D32 FPGA108
184 GND
185 B2 IO DIFFIO_RX48n D31 FPGA109
186 B2 IO DIFFIO_TX48p J27 FPGA110
187 GND
188 B2 IO DIFFIO_TX48n J26 FPGA111
189 GND
190 B2 IO DIFFIO_RX47p F30 FPGA112
191 B2 IO DIFFIO_RX47n F29 FPGA113
192 GND
193 B2 IO DIFFIO_TX47p L28 FPGA114
194 GND
195 B2 IO DIFFIO_TX47n L27 FPGA115
196 B2 IO DIFFIO_RX46p G30 FPGA116
197 GND
198 B2 IO DIFFIO_RX46n G29 FPGA117
199 GND
Table 3-3. J10 (female) Pin Assignment Table
J10 Pin
FPGA
Bank FPGA Pin
Function Other FPGA Pin
Information
FPGA Ball Board Net
1 B2 IO DIFFIO_TX46p L26 FPGA118
2 GND
3 B2 IO DIFFIO_TX46n L25 FPGA119
4 GND
5 B2 IO DIFFIO_RX45p H30 FPGA120
6 B2 IO DIFFIO_RX45n H29 FPGA121
7 GND
8 B2 IO DIFFIO_TX45p L24 FPGA122
9 GND
10 B2 IO DIFFIO_TX45n L23 FPGA123
11 B2 IO DIFFIO_RX44p J30 FPGA124
12 GND
Table 3-2. J-8 (male) Pin Assignment Table (Continued)
J8 Pin
FPGA
Bank FPGA Pin
Function Other FPGA Pin
Information
FPGA Ball Board Net