Atmel AT91CAP9, User Manual

Page: 159 / 180

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SODIMM_DQS[0..1]
SODIMM_D[0..31]
SODIMM_C[0..53]
SODIMM_S[0..18]
UGRID[0..75]
VDDIOP1
M
P
IO
A
[0
..
3
1
]
M
P
IO
B
[0
..
4
4
]
PISMO_AUX[0..12]
PISMO_DM_DA[0..7]
PISMO_DM_DB[0..7]
PISMO_DM_DC[0..7]
PISMO_DM_DD[0..7]
PISMO_FS[0..9]
PISMO_DM_DQSD_DH
PISMO_SM[0..88]
PISMO_DM_DQSC_DH
PISMO_DM_DQSB_DH
PISMO_DM_DQSA_DH
PISMO_DM[0..36]
PISMO_DM_DQSD_DL
PISMO_DM_DQSC_DL
PISMO_DM_DQSB_DL
PISMO_DM_DQSA_DL
PISMO_NA[0..26]
FPGA[0..275]
VCCIO_1
VCCIO_2
VCCIO_3
NRST
FPGA[0..275]
VDDIOP1
PD16_D16
PD15_NCS3_NANDCS
PD8_NCS5_CFCS1
PD18_D18
PD10_CFCE2
PD9_CFCE1 PD9_CFCE1
PD13_A24
PD30_D30
PD29_D29
PD28_D28
PD27_D27
PD21_D21
PD20_D20
PD31_D31
PD25_D25
PD24_D24
PD23_D23
PD22_D22
SDWE
SDDRCS
SDDRCKE
NWR3
A[0..22]
D[0..15]
NCS[0..1]
N
R
S
T
DQS[0..1]
NRD
RAS
CAS
BCCLK
OWAIT
SDA10
NWR0
NWR1
SDDRCLKN
SDDRCLK
NANDWE
NANDOE
PD6_NWAIT
PA[0..31]
PC[0..31]
PD[0..5]
VCCIO_1
VCCIO_6
VCCIO_7
VCCIO_2
VCCIO_3
VCCIO_4
VCCIO_5
VCCIO_8
PD6_NWAIT
PD7_NCS4_CFCS0
PD7_NCS4_CFCS0
PD8_NCS5_CFCS1
PD9_CFCE1
PD11_NCS2
PD12_A23
PD14_A25_CFRNW
PD17_D17
PD19_D19
PD26_D26
PD[0..5]
PA[0..31]
PB[0..31]
PC[0..31]
HDPA
HDMA
HDPB
HDMB
HDPA
HDMA
HDPB
HDMB
SHDN
S
H
D
N
VCCIO_8
RVDD_EBICAP
S
2
_
T
C
K
S
2
_
T
M
S
S
2
_
T
D
I
S
2
_
T
D
O
CONFIG_DONE
nCONFIG
nCE
nCSO
ASDO
DATA0
DCLK
PD10_CFCE2
PD22_D22
PD12_A23
PD17_D17
PD20_D20
PD23_D23
PD13_A24
PD18_D18
PD21_D21
PD24_D24
PD14_A25_CFRNW
PD26_D26
PD27_D27
PD28_D28
PD29_D29
PD15_NCS3_NANDCS
PD25_D25
PD30_D30
PD16_D16
PD11_NCS2
PD19_D19
PD31_D31
VCCIO_5
VCCIO_6
VCCIO_4
VCCIO_6
VCCIO_7
VCCIO_8
RVDD_EBICAP
PB4
PB5
PB[0..31]
VDDIOP0
VDDIOM
VDDIOM
VDDIOP0
NRST
3V3
1V2
5V
3V3
2V5
1V8
3V3
1V2
3V3
2V5
1V8
5V
1V2
3V3
3V3 2V5 1V8
3V3
5V
REV DATE MODIF.
DES. DATE
VER.
SCALE 1/1 REV. SHEET
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
INIT EDIT A
AT91CAP9A-DKZ
1
14
XX-SEP-06
B
XX-XXX-06 YRDE XXX
MEZZANINE BOARD
B
04-MAY-07 YRDE
REV DATE MODIF.
DES. DATE
VER.
SCALE 1/1 REV. SHEET
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
INIT EDIT A
AT91CAP9A-DKZ
1
14
XX-SEP-06
B
XX-XXX-06 YRDE XXX
MEZZANINE BOARD
B
04-MAY-07 YRDE
REV DATE MODIF.
DES. DATE
VER.
SCALE 1/1 REV. SHEET
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
INIT EDIT A
AT91CAP9A-DKZ
1
14
XX-SEP-06
B
XX-XXX-06 YRDE XXX
MEZZANINE BOARD
B
04-MAY-07 YRDE
TOP LEVEL
U2
U7
page 4
page 14
page 2
page 13
page 3
pages 5, 6, 7
pages 9, 10, 11, 12
U8
J1 & J2
page 8
J3
J4
J5
FD1_2007_05_04_15H00
FEED = NO
FIDU
FD1_2007_05_04_15H00
FEED = NO
FIDU
FD3
FEED = NO
FIDU
FD3
FEED = NO
FIDU
CONFIG
13_CONFIG
VCCIO_8
S
2
_
T
C
K
S
2
_
T
M
S
S
2
_
T
D
O
S
2
_
T
D
I
DCLK
nCONFIG
nCSO
DATA0
GND
3V3
nCE
CONFIG_DONE
ASDO
FD4
FEED = NO
FIDU
FD4
FEED = NO
FIDU
FPGA_SODIMM
14_FPGA_SODIMM
VCCIO_6
VCCIO_7
S
O
D
IM
M
_
C
[0
..
5
3
]
GND
S
O
D
IM
M
_
S
[0
..
1
8
]
S
O
D
IM
M
_
D
Q
S
[0
..
1
]
S
O
D
IM
M
_
D
[0
..
3
1
]
5V
FPGA
09_FPGA
FPGA[0..275]
PISMO_NA[0..26]
PISMO_SM[0..88]
PISMO_AUX[0..12]
SODIMM_S[0..18]
PISMO_DM_DQSA_DH
PISMO_DM_DQSA_DL
PISMO_DM_DQSB_DL
PISMO_DM_DQSB_DH
PISMO_DM_DQSC_DL
PISMO_DM_DQSC_DH
PISMO_DM_DQSD_DL
PISMO_DM_DQSD_DH
PISMO_FS[0..9]
PISMO_DM[0..36]
PISMO_DM_DA[0..7]
PISMO_DM_DB[0..7]
PISMO_DM_DC[0..7]
PISMO_DM_DD[0..7]
SODIMM_C[0..53]
SODIMM_D[0..31]
SODIMM_DQS[0..1]
M
P
IO
A
[0
..
3
1
]
N
R
S
T
M
P
IO
B
[0
..
4
4
]
VCCIO_8
VCCPD
VCCINT
VCCIO_4
VCCIO_6
VCCIO_7
GND
3V3
2V5
1V8
VCCIO_1
VCCIO_2
VCCIO_3
VCCIO_5
S2_TDO
S2_TDI
S2_TMS
S2_TCK
D
A
T
A
0
n
C
S
O
n
C
E
D
C
L
K
n
C
O
N
F
IG
UGRID[0..75]
C
O
N
F
IG
_
D
O
N
E
A
S
D
O
PCB1 PCB1
FD2
FEED = NO
FIDU
FD2
FEED = NO
FIDU
FD1
FEED = NO
FIDU
FD1
FEED = NO
FIDU
P
IS
M
O
2
04_PISMO2_CONNECTOR
2
V
5
1
V
8
VCCIO_4
VCCIO_5
VCCIO_6
GND
3
V
3
PISMO_AUX[0..12]
PISMO_DM_DB[0..7]
PISMO_DM_DA[0..7]
PISMO_DM_DC[0..7]
PISMO_DM_DD[0..7]
PISMO_FS[0..9]
PISMO_DM_DQSD_DH
PISMO_SM[0..88]
PISMO_DM_DQSC_DH
PISMO_DM_DQSB_DH
PISMO_DM_DQSA_DH
PISMO_DM_DQSD_DL
PISMO_DM_DQSC_DL
PISMO_DM_DQSB_DL
PISMO_DM_DQSA_DL
PISMO_NA[0..26]
PISMO_DM[0..36]
M
O
T
H
E
R
B
O
A
R
D
C
O
N
N
E
C
T
O
R
S
03_MOTHERBOARD_CONNECTORS
FPGA[0..275]
WKUP
HDMA
VDDIOP1
HDMB
PC[0..31]
NRST
PA[0..31]
PB[0..31]
HDPA
SHDN
HDPB
2V5
1V8
GND
1V2
5V
3V3
PD24_D24
PD15_NCS3_NANDCS
PD25_D25
PD11_NCS2
PD10_CFCE2
PD[0..5]
PD7_NCS4_CFCS0
PD26_D26
PD9_CFCE1
PD27_D27
PD16_D16
PD30_D30
PD28_D28
PD17_D17
PD31_D31
PD20_D20
PD14_A25_CFRNW
PD6_NWAIT
PD29_D29
PD18_D18
PD8_NCS5_CFCS1
PD21_D21
PD19_D19
PD12_A23
PD22_D22
PD13_A24
PD23_D23
VCCIO_1
VCCIO_2
VCCIO_3
USER_GRID
02_USER_GRID
UGRID[0..75]
GND
3V3
FD5
FEED = NO
FIDU
FD5
FEED = NO
FIDU
C
A
P
_
S
O
D
IM
M
08_CAP_SODIMM
OWAIT
SDDRCLKN
CAS
SDWE
NANDOE
PD24_D24
PD15_NCS3_NANDCS
VDDIOM
SDDRCKE
PD25_D25
PD11_NCS2
PD10_CFCE2
PD7_NCS4_CFCS0
PD26_D26
PD9_CFCE1
PD27_D27
PD16_D16
SDDRCLK
PD30_D30
D[0..15]
NWR0
PD28_D28
PD17_D17
NCS[0..1]
NWR1
NANDWE
PD31_D31
PD20_D20
PD14_A25_CFRNW
PD6_NWAIT
DQS[0..1]
SDA10
PD29_D29
PD18_D18
PD8_NCS5_CFCS1
A[0..22]
NWR3
PD21_D21
NRD
PD19_D19
PD12_A23
BCCLK
PD22_D22
SDDRCS
RAS
PD13_A24
PD23_D23
GND
RVDD_EBICAP
VDDIOP0
PB4
PB5
NRST
CAP
05_AT91CAP
SDDRCLKN
CAS
OWAIT
VDDIOP1
PD24_D24
PD15_NCS3_NANDCS
SDWE
NANDOE
HDMA
VDDIOM
M
P
IO
B
[0
..
4
4
]
HDMB
P
C
[0
..
3
1
]
P
D
[0
..
5
]
PD25_D25
PD11_NCS2
PD10_CFCE2
SDDRCKE
P
D
7
_
N
C
S
4
_
C
F
C
S
0
PD26_D26
N
R
S
T
P
D
9
_
C
F
C
E
1
PD27_D27
PD16_D16
P
A
[0
..
3
1
]
PD30_D30
SDDRCLK
D
[0
..
1
5
]
PD28_D28
PD17_D17
NWR0
N
C
S
[0
..
1
]
PD31_D31
PD20_D20
PD14_A25_CFRNW
P
D
6
_
N
W
A
IT
NWR1
S
H
D
N
NANDWE
D
Q
S
[0
..
1
]
GND
PD29_D29
PD18_D18
P
D
8
_
N
C
S
5
_
C
F
C
S
1
SDA10
A
[0
..
2
2
]
PD21_D21
NWR3
1V2
PD19_D19
PD12_A23
NRD
P
B
[0
..
3
1
]
PD22_D22
BCCLK
PD13_A24
M
P
IO
A
[0
..
3
1
]
SDDRCS
RAS
HDPA
PD23_D23
HDPB
3V3
5V
VCCIO_8
RVDD_EBICAP
VDDIOP0