Atmel AT91CAP9, User Manual

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6-2 AT91CAP9A-DK Development Kit User Guide
6321B–CAP–02-Jul-07
6.3.2 FPGA Specific (Altera Stratix-II EP2S90F1020C5)
„ EPCS64SI16N configuration memory
„ ByteBlaster configuration header
„ JTAG header
„ Reconfiguration push button
„ 80-pad, 1.27 mm-spaced user IO grid
„ Four user LEDs
„ PISMO-II standard extension connector
„ FPGA extension port (EBI memory module or custom application), SODIMM-144 format
Figure 6-1. AT91CAP9A-DKZ Mezzanine Board Layout - Top View
6.4 Powering Up the Board
A complete AT91CAP9A-DK system is powered through the AT91CAP-DKM motherboard via a stan-
dard ATX PC power supply.
The power control signal is connected to the SHDN signal, generated by the AT91CAP9 chip from the
AT91CAP9A-DKZ mezzanine board.
High Speed
Host USB port
FPGA configuration
memory port
("Byte Blaster")
FPGA configuration
memory
FPGA extension
PISMO-II format
FPGA clock sources
oscillator and SMB
FPGA extension
(EBI bus or custom application)
SODIMM-144 format
CAP backup
battery
CAP memory extension
(EBI bus)
SODIMM-144 format
CAP ICE
interface
System
reset
button
CAP
wake-up
button
User IO grid
User LEDs
FPGA JTAG
interface
ALTERA
Stratix-II
FPGA
CAP9 chip
FPGA reconfiguration
push-button