Atmel AT91CAP9, User Manual

Page: 48 / 180

7-2 AT91CAP9A-DK Development Kit User Guide
6321B–CAP–02-Jul-07
7.1 Block Diagram
Figure 7-1. AT91CAP9A-DKZ Mezzanine Block Diagram (see the complete schematic in Section 16 )
SODIM
M
_
DQS[0
..1
]
SODIM
M
_
D[0
..3
1
]
SODIM
M
_
C[0
..5
3
]
SODIM
M
_
S[0..18]
UGRID[0
..7
5
]
VDDIOP1
MP IOA[0..31]
MP IOB[0..44]
PISM
O_AUX
[0..12]
PISM
O_DM
_DA[0..7]
PISM
O_DM
_DB[0..7]
PISM
O_
DM
_
DC[0
..7
]
PISM
O_
DM
_
DD[0
..7
]
PISM
O
_
FS[0..9]
PISM
O_
DM
_
D
QSD_
DH
PISM
O_SM
[0..88]
PISM
O_
DM
_
D
QSC_
DH
PISM
O_DM
_DQSB_DH
PISM
O_DM
_DQSA_DH
PISM
O_DM
[0..36]
PISM
O_
DM
_
D
QSD_
DL
PISM
O_
DM
_
D
QSC_
DL
PISM
O_DM
_DQSB_DL
PISM
O_DM
_DQSA_DL
PISM
O_NA[0..26]
FPG
A
[0..275]
VCCIO_
1
VCCIO_
2
VCCIO_
3
NRST
FPG
A
[0..275]
VDDIOP1
PD
16_D
16
PD1
5
_
NCS3
_
N
ANDCS
PD
8_N
C
S
5_C
FC
S1
PD
18_D
18
PD
10_C
FC
E2
PD9_CFCE1PD9_CFCE1 PD
13_A24
PD
30_D
30
PD
29_D
29
PD
28_D
28
PD
27_D
27
PD
21_D
21
PD
20_D
20
PD
31_D
31
PD
25_D
25
PD
24_D
24
PD
23_D
23
PD
22_D
22
SDW
E
SDDRCS SDDRCKE NW
R3
A[0..22] D
[0..15]
NCS[0..1]
NRST
DQ
S[0..1]
NRD RAS CAS BCCL
K
OW
AI
T
SDA10 NW
R0
NW
R1
SDDRCL
KN
SDDRCL
K
NANDW
E
NANDOE
PD
6_N
W
A
IT
PA[0..31]
PC[0..31]
PD[0..5]
VCCIO_
1
VCCIO_
6
VCCIO_
7
VCCIO_
2
VCCIO_
3
VCCIO_
4
VCCIO_
5
VCCIO_
8
PD
6_N
W
A
IT
PD
7_N
C
S
4_C
FC
S0
PD
7_N
C
S
4_C
FC
S0
PD
8_N
C
S
5_C
FC
S1
PD9_CFCE1
PD
11_N
C
S
2
PD
12_A23
PD
14_A25_C
FR
N
W
PD
17_D
17
PD
19_D
19
PD
26_D
26
PD[0..5] PA[0..31] PB[0..31] PC[0..31]
HDPA HDM
A
HDPB HDM
B
HDPA HDM
A
HDPB HDM
B
SHDN
SHDN
VCCIO_8
RVDD_
EBICAP
S2_TCK
S2_TMS
S2_TDI
S2_TDO
CONFIG_
D
ONE
nC
O
N
FIG
nC
E
nC
SO
ASDO DAT
A
0
DCL
K
PD
10_C
FC
E2
PD
22_D
22
PD
12_A23
PD
17_D
17
PD
20_D
20
PD
23_D
23
PD
13_A24
PD
18_D
18
PD
21_D
21
PD
24_D
24
PD
14_A25_C
FR
N
W
PD
26_D
26
PD
27_D
27
PD
28_D
28
PD
29_D
29
PD1
5
_
NCS3
_
N
ANDCS
PD
25_D
25
PD
30_D
30
PD
16_D
16
PD
11_N
C
S
2
PD
19_D
19
PD
31_D
31
VCCIO_5 VCCIO_6 VCCIO_4
VCCIO_
6
VCCIO_
7
VCCIO_
8
RVDD_
EBICAP
PB4 PB5
PB[0..31]
VDDIOP0 VDDIOM
VDDIOM VDDIOP0
NRST
3V3 1V2 5V
3V3 2V5 1V8 3V3 1V2
3V3 2V5 1V8
5V
1V2
3V3
3V3
2V5
1V8
3V3
5V
U2
U7
page
4
page
14
page
2
page
13
page
3
pages
5,
6,
7
pages
9,
10,
11,
12
U8
J
1&J
2
page
8
J3
J4 J5
CONFIG
13_C
O
N
FIG
VCCIO_8
S2_TCK
S2_TMS
S2_TDO
S2_TDI
DCLK
nCONFI
G
nCS
O
DAT
A
0
GND 3V
3
nCE
CONF
IG_DONE
ASDO
FPGA_SODIMM
14_FPG
A_SO
D
IM
M
VCCIO_6 VCCIO_7
SO DIM M_ C[0. .53]
GND
SOD IMM_ S[0..1 8]
SO DIM M_ DQS[0. .1 ]
SO DIM M_ D[0. .31]
5V
FPGA
09_FPG
A
FP
GA
[0
..
275]
PISM
O
_
NA[0
..2
6
]
PISM
O
_
SM
[0
..8
8
]
PISM
O
_
AUX
[0
..1
2
]
S
O
DI
MM_S
[0.
.18]
PISM
O
_
DM
_
D
Q
SA_
DH
PISM
O
_
DM
_
D
Q
SA_
DL
PISM
O
_
DM
_
D
Q
SB_
DL
PISM
O
_
DM
_
D
Q
SB_
DH
PISM
O_DM
_DQSC_DL
PISM
O_DM
_DQSC_DH
PISM
O_DM
_DQSD_DL
PISM
O_DM
_DQSD_DH
PISM
O
_
F
S
[0
..9
]
PISM
O
_
DM
[0
..3
6
]
PISM
O
_
DM
_
D
A[0
..7
]
PISM
O
_
DM
_
D
B[0
..7
]
PISM
O_DM
_DC[0..7]
PISM
O_DM
_DD[0..7]
S
O
DI
MM_C[
0.
.53]
S
O
DI
MM_D[
0.
.31]
SODIM
M
_
DQS[0..1]
MPIO A[0. .31]
NRST
MPIO B[0. .44]
VCCIO_8 VCCPD VCCINT VCCIO_4 VCCIO_6 VCCIO_7 GND 3V
3
2V
5
1V
8
VCCIO_1 VCCIO_2 VCCIO_3 VCCIO_5 S
2_T
DO
S
2_T
DI
S
2_T
MS
S
2_T
CK
DAT A0
nCSO
nCE
DCLK
nCONFIG
UGRID[0..75]
CONFIG _DONE
ASDO
PISMO2
04_PISM
O
2_C
O
N
N
E
C
T
O
R
2V5
1V8
VCCIO_4 VCCIO_5 VCCIO_6
GND
3V3
PISM
O
_
AUX
[0
..1
2
]
PISM
O
_
DM
_
D
B[0
..7
]
PISM
O
_
DM
_
D
A[0
..7
]
PISM
O_DM
_DC[0..7]
PISM
O_DM
_DD[0..7]
PISM
O
_
F
S
[0
..9
]
PISM
O_DM
_DQSD_DH
PISM
O
_
SM
[0
..8
8
]
PISM
O_DM
_DQSC_DH
PISM
O
_
DM
_
D
Q
SB_
DH
PISM
O
_
DM
_
D
Q
SA_
DH
PISM
O_DM
_DQSD_DL
PISM
O_DM
_DQSC_DL
PISM
O
_
DM
_
D
Q
SB_
DL
PISM
O
_
DM
_
D
Q
SA_
DL
PISM
O
_
NA[0
..2
6
]
PISM
O
_
DM
[0
..3
6
]
USER_GRID
02_U
SER
_G
R
ID
UGRID[0..75]
GND
3V
3
MOTHERBOARD CONNECTORS
03_M
O
T
H
E
R
B
O
A
R
D
_
C
O
N
N
E
C
T
O
R
S
FP
GA
[0
..
275]
WK
U
P
HDM
A
VDDIOP1
HDM
B
PC[0
..3
1
]
NRST
P
A
[0.
.31]
P
B
[0.
.31]
HDPA SHDN HDPB
2V
5
1V
8
GND 1V
2
5V 3V
3
P
D
24_D24
PD15_NCS3_NANDCS
P
D
25_D25
P
D
11_NCS
2
P
D
10_CFCE
2
PD[0
..5
]
P
D
7_NCS
4_CFCS
0
P
D
26_D26
PD9
_
C
F
C
E1
P
D
27_D27
P
D
16_D16
P
D
30_D30
P
D
28_D28
P
D
17_D17
P
D
31_D31
P
D
20_D20
P
D
14_A
25_CFRNW
P
D
6_NW
A
IT
P
D
29_D29
P
D
18_D18
P
D
8_NCS
5_CFCS
1
P
D
21_D21
P
D
19_D19
P
D
12_A
23
P
D
22_D22
P
D
13_A
24
P
D
23_D23
VCCIO_1 VCCIO_2 VCCIO_3
CAP_SODIMM
08_C
AP_SO
D
IM
M
OW
A
IT
SDDRCLKN
CAS
SDW
E
NANDOE
P
D
24_D24
PD15_NCS3_NANDCS
VDDIOM
SDDRCKE P
D
25_D25
P
D
11_NCS
2
P
D
10_CFCE
2
P
D
7_NCS
4_CFCS
0
P
D
26_D26
PD9
_
C
F
C
E1
P
D
27_D27
P
D
16_D16
SDDRCLK P
D
30_D30 D[
0.
.15]
NW
R0
P
D
28_D28
P
D
17_D17
NCS[0..1]
NW
R1
NANDW
E
P
D
31_D31
P
D
20_D20
P
D
14_A
25_CFRNW
P
D
6_NW
A
IT
DQ
S[0
..1
]
SDA1
0
P
D
29_D29
P
D
18_D18
P
D
8_NCS
5_CFCS
1
A
[0.
.22]
NW
R3
P
D
21_D21
NRD
P
D
19_D19
P
D
12_A
23
BCCLK
P
D
22_D22
SDDRCS
RAS
P
D
13_A
24
P
D
23_D23
GND
RVDD_EBICAP
VDDIOP0
PB4 PB5
NRST
CAP
05_AT
91C
AP
SDDRCLKN CAS OW
A
IT
VDDIOP1
P
D
24_D24
PD15_NCS3_NANDCS SDW
E
NANDOE
HDM
A
VDDIOM
MPIOB[0 ..44 ]
HDM
B
PC[0 ..31 ]
PD[0 ..5]
P
D
25_D25
P
D
11_NCS
2
P
D
10_CFCE
2
SDDRCKE
PD 7_NCS4_CFCS 0
P
D
26_D26
NRST
PD9 _C FCE1
P
D
27_D27
P
D
16_D16
PA [0. .31]
P
D
30_D30
SDDRCLK
D[0. .15]
P
D
28_D28
P
D
17_D17
NW
R0
NCS[0. .1 ]
P
D
31_D31
P
D
20_D20
P
D
14_A
25_CFRNW
PD 6_NWAIT
NW
R1
SHD N
NANDW
E
DQS[0. .1 ]
GND
P
D
29_D29
P
D
18_D18
PD 8_NCS5_CFCS 1
SDA1
0
A[0. .22]
P
D
21_D21
NW
R3
1V
2
P
D
19_D19
P
D
12_A
23
NRD
PB [0. .31]
P
D
22_D22
BCCLK P
D
13_A
24
MPIOA[0 ..31 ]
SDDRCS RAS
HDPA
P
D
23_D23
HDPB
3V
3
5V
VCCIO_8
RVDD_EBICAP
VDDIOP0