Instruction Cycle Timings
ARM DDI 0210C
Copyright © 2001, 2004 ARM Limited. All rights reserved.
6-13
Note
Operations where the destination is the PC are not available in Thumb state.
4
pc’
2
0
(pc’)
0
1
0
c
5
pc’+4
2
0
(pc’+4)
0
1
0
c
pc’+8
Table 6-9 Load register instruction cycle operations (continued)
Operation type
Cycle
Address
MAS[1:0]
nRW
Data
nMREQ
SEQ
nOPC
nTRANS
Table 6-10 MAS[1:0] signal encoding
Bit [1]
Bit [0]
Data size
0
0
byte
0
1
halfword
1
0
word
1
1
reserved
Summary of Contents for ARM7TDMI
Page 6: ...Contents vi Copyright 2001 2004 ARM Limited All rights reserved ARM DDI 0210C ...
Page 10: ...List of Tables x Copyright 2001 2004 ARM Limited All rights reserved ARM DDI 0210C ...
Page 14: ...List of Figures xiv Copyright 2001 2004 ARM Limited All rights reserved ARM DDI 0210C ...
Page 46: ...Introduction 1 26 Copyright 2001 2004 ARM Limited All rights reserved ARM DDI 0210C ...
Page 120: ...Coprocessor Interface 4 18 Copyright 2001 2004 ARM Limited All rights reserved ARM DDI 0210C ...
Page 142: ...Debug Interface 5 22 Copyright 2001 2004 ARM Limited All rights reserved ARM DDI 0210C ...
Page 282: ...Glossary Glossary 6 Copyright 2001 2004 ARM Limited All rights reserved ARM DDI 0210C ...