•
PLL Lock: Shows the PLL locked or unlocked state.
•
Pattern Sync: Shows the pattern synced or not synced state. The pattern is
considered synced when the start of he data data sequence is detected.
•
Details: Shows the PLL lock and pattern sync detailed information per channel.
Port
Allows you to specify the interface to test. The following port are available to test:
•
XCVR
•
CMOS
PMA Settings
Allows you to make changes to the PMA parameters that affect the active transceiver
interface. The following settings are available for analysis:
6. Board Test System
UG-20046 | 2018.07.20
Intel
®
Stratix
®
10 GX FPGA Development Kit User Guide
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