Altera Stratix 10 GX FPGA User Manual Download Page 53

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Attention:

Using the Quartus Programmer to program a device on the board causes other JTAG-

based applications such as the Board Test System and the Power Monitor to lose their

connection to the board. Restart those applications after programming is complete.

4. Board Components

UG-20046 | 2018.07.20

Intel

Stratix

10 GX FPGA Development Kit User Guide

Summary of Contents for Stratix 10 GX FPGA

Page 1: ...Intel Stratix 10 GX FPGA Development Kit User Guide Subscribe Send Feedback UG 20046 2018 07 20 Latest document on the web PDF HTML...

Page 2: ...put Output Components 27 4 5 1 User Defined Push Buttons 27 4 5 2 User Defined DIP Switches 27 4 5 3 User Defined LEDs 27 4 6 Components and Interfaces 29 4 6 1 PCI Express 29 4 6 2 10 100 1000 Ethern...

Page 3: ...XCVR Tab 73 6 3 6 The PCIe Tab 76 6 3 7 The FMC Tab 79 6 3 8 The DDR3 Tab 83 6 3 9 The DDR4 Tab 85 6 3 10 Power Monitor 86 6 3 11 Clock Controller 88 A Additional Information 91 A 1 Safety and Regula...

Page 4: ...Download Cable II PHY SGMII RJ 45 10 100 1000 Ethernet MAX V System Controller x16 x4 x1 x4 x16 LTM2987 Power Manager Power Regulators UG 20046 2018 07 20 Intel Corporation All rights reserved Intel...

Page 5: ...k fan 200 W 1 3 Handling the Board When handling the board it is important to observe static discharge precautions Caution Without proper anti static handling the board can be damaged Therefore use an...

Page 6: ...ense identify specific users and computers and obtain and install license file If you already have a licensed version of the Standard Edition or Pro Edition you can use that license file with this kit...

Page 7: ...e Pro Edition 2 2 Development Board Package Download the Intel Stratix 10 FPGA Development Kit package from the Intel Stratix 10 FPGA Development Kit page of the Intel website Unzip the Intel Stratix...

Page 8: ...Cable II driver on the host computer Installation instrcutions for the On Board Intel FPGA Download Cable II driver for your operating system are available on the Intel website On the Altera Programmi...

Page 9: ...nect the supplied power supply to an outlet and the DC Power Jack J27 on the FPGA board Note Use only the supplied power supply Power regulation circuits on the board can be damaged by power supplies...

Page 10: ...r PCIe x4 OFF 3 x8 ON for PCIe x8 OFF 4 x16 ON for PCIe x16 ON 2 If all of the resistors are open the FMC VCCIO value is 1 2 V To change that value add resistors as shown in the folowing table Table 4...

Page 11: ...st Mode MSEL2 MSEL1 0 1 QSPI AS Normal Mode MSEL2 MSEL1 1 0 AVST x16 Mode Default MSEL2 MSEL1 1 1 JTAG Only Mode 2 MSEL1 5 Set DIP switch bank SW6 to match the following table Table 7 SW3 DIP Switch D...

Page 12: ...REFCLK frequency to 148 5 MHz OFF Table 9 SW8 DIP Switch Default Settings Board Bottom Switch Board Label Function Default Position 1 I2C_SDA Connects VRM I2C to MAX V I2C chain ON 2 I2C_SCL Connects...

Page 13: ...art of the Board Test System BTS GUI that is under development It will be updated in a future version when new information is available 3 Development Board Setup UG 20046 2018 07 20 Intel Stratix 10 G...

Page 14: ...s and logos are trademarks of Intel Corporation or its subsidiaries in the U S and or other countries Intel warrants performance of its FPGA and semiconductor products to current specifications in acc...

Page 15: ...t loads from flash memory to the FPGA This button resides on the LED daughter board S1 Program configuration push button Configures the FPGA from flash memory image based on the program LEDs This butt...

Page 16: ...12 D13 FMC LEDs Illuminates for RX TX PRNSTn activity of the FMC daughter card when present These LEDs reside on the LED daughter board Clock Circuits X1 SDI Reference Clock SW4 2 DIP switch controlle...

Page 17: ...33 MHz DDR3 memory x72 1066 MHz RLDRAM3 memory x36 1200 MHz U12 U83 Flash Memory ICS 1GBIT STRATA FLASH 16 BIT DATA Communication Ports J9 PCI Express x16 edge connector Gold plated edge fingers for u...

Page 18: ...to power ON or OFF the board when supplied from the DC input jack J26 PCIe 2x4 ATX power connector 12 V ATX input This input must be connected to the 8 pin Aux PCIe power connector provided by the PC...

Page 19: ...Intel MAX 10 Intel FPGA Download Cable bus USB_CFG3 K5 1 8V MAX V to Intel MAX 10 Intel FPGA Download Cable bus USB_CFG4 L1 1 8V MAX V to Intel MAX 10 Intel FPGA Download Cable bus USB_CFG5 L2 1 8V MA...

Page 20: ...select MAX_RESETn C5 2 5V MAX V reset signal Si516_FS A4 2 5V Si516 device frequency select signal OVERTEMP E1 2 5V FAN PWM control signal CLK0_FINC E9 2 5V Si5341A device frequency increment signal...

Page 21: ...1 8V Flash address bus FLASH_ADDR15 C15 1 8V Flash address bus FLASH_ADDR16 H3 1 8V Flash address bus FLASH_ADDR17 H2 1 8V Flash address bus FLASH_ADDR18 E13 1 8V Flash address bus FLASH_ADDR19 F13 1...

Page 22: ...4 1 8V Flash address valid FLASH_CEn1 F11 1 8V Flash chip enable 1 FPGA_PR_ERROR K12 1 8V Partial reconfiguration error signal FPGA_CvP_CONFDONE M14 1 8V CvP configuration done signal FLASH_RDYBSYn1 P...

Page 23: ...5_BEn2 T12 1 8V MAX V byte enable MAX5_BEn3 P10 1 8V MAX V byte enable CPU_RESETn K4 1 8V CPU reset button I2C_1 8V_SCL P13 1 8V 1 8V I2C bus I2C_1 8V_SDA R14 1 8V 1 8V I2C bus OVERTEMPn_1 8V N13 1 8V...

Page 24: ...n the progress bar reaches 100 Using the Quartus Programmer to configure a device on the board causes other JTAG based applications such as the Board Test System and the Power Monitor to lose their co...

Page 25: ...LED Daughter Board MAX 10 Intel FPGA Download Cable II U23 S10_JTAG MAX V System Controller U11 M5_JTAG FMCA J13 FMCA_JTAG External JTAG USB JTAG Header from LED Daughter Board Dedicated USB MAX 10 JT...

Page 26: ...oard PGM_LED2 2 5V D13 on the LED board FMCA_PRSTn 1 8V D15 on the LED board PCIE_LED_X1 1 8V D17 on the LED board PCIE_LED_X4 1 8V D19 on the LED board PCIE_LED_X8 1 8V D20 on the LED board PCIE_LED_...

Page 27: ...h There are no board specific functions for these switches When the switch is in the OFF position logic 1 is selected When the switch is in the ON position logic 0 is selected Table 14 User defined DI...

Page 28: ...LED board USER_LED_G3 D19 1 8V D4 on LED board USER_LED_R0 B18 1 8V D7 on LED board USER_LED_R1 F17 1 8V D9 on LED board USER_LED_R2 E18 1 8V D10 on LED board USER_LED_R3 E19 1 8V 4 Board Components U...

Page 29: ...tix 10 development board Although the board can also be powered by a laptop power supply for use on a lab bench Intel recommends that you do not power up from both supplies at the same time Ideal diod...

Page 30: ...4 V PCML Receive bus B55 PCIE_RX_N9 AY44 1 4 V PCML Receive bus B59 PCIE_RX_N10 AU42 1 4 V PCML Receive bus B63 PCIE_RX_N11 AV44 1 4 V PCML Receive bus B67 PCIE_RX_N12 AR42 1 4 V PCML Receive bus B71...

Page 31: ..._CN9 AW46 1 4 V PCML Transmit bus A61 PCIE_TX_CN10 AY48 1 4 V PCML Transmit bus A65 PCIE_TX_CN11 AU46 1 4 V PCML Transmit bus A69 PCIE_TX_CN12 AV48 1 4 V PCML Transmit bus A73 PCIE_TX_CN13 AR46 1 4 V...

Page 32: ...applications The Marvell 88E1111 PHY uses a 2 5V and 1 0V power rails and requires a 25 MHz reference clock driven from a dedicated oscillator The PHY interfaces to a HALO HFJ11 1G02E model RJ45 with...

Page 33: ...Media dependent interface 42 MDI_P3 2 5V Media dependent interface 4 6 3 HiLo External Memory Interface This section describes the Intel Stratix 10 GX FPGA development board s external memory interfac...

Page 34: ...table N2 MEM_ADDR_CMD18 R36 Adjustable L4 MEM_ADDR_CMD19 L35 Adjustable P5 MEM_ADDR_CMD20 L40 Adjustable M5 MEM_ADDR_CMD21 K40 Adjustable P1 MEM_ADDR_CMD22 G38 Adjustable R4 MEM_ADDR_CMD23 H38 Adjusta...

Page 35: ...3 Adjustable A4 MEM_DQA0 B27 Adjustable B4 MEM_DQA1 F27 Adjustable B5 MEM_DQA2 G27 Adjustable B6 MEM_DQA3 C27 Adjustable A8 MEM_DQA4 C26 Adjustable B8 MEM_DQA5 B25 Adjustable B9 MEM_DQA6 D26 Adjustabl...

Page 36: ...justable J16 MEM_DQB1 K33 Adjustable K16 MEM_DQB2 N33 Adjustable L16 MEM_DQB3 M33 Adjustable H17 MEM_DQB4 J34 Adjustable K17 MEM_DQB5 N32 Adjustable K18 MEM_DQB6 N31 Adjustable L18 MEM_DQB7 M34 Adjust...

Page 37: ..._N T32 Adjustable V4 MEM_DQS_ADDR_CMD_P R32 Adjustable A7 MEM_DQSA_N0 F26 Adjustable A3 MEM_DQSA_N1 K26 Adjustable A15 MEM_DQSA_N2 V27 Adjustable G18 MEM_DQSA_N3 R27 Adjustable A6 MEM_DQSA_P0 E26 Adju...

Page 38: ...e a variable voltage of 1 2V 1 35V 1 5V and 1 8V default Table 19 FMC Connector Pin Assignments Board Reference Schematic Signal Name FPGA Pin Number I O Standard D1 FMCA_C2M_PG H5 FMCA_CLK_M2C_N0 AT1...

Page 39: ...P14 AT1 1 4V PCML K37 FMCA_DP_C2M_P15 AP1 1 4V PCML C7 FMCA_DP_M2C_N0 BH10 1 4V PCML A3 FMCA_DP_M2C_N1 BJ8 1 4V PCML A7 FMCA_DP_M2C_N2 BG8 1 4V PCML A11 FMCA_DP_M2C_N3 BE8 1 4V PCML A15 FMCA_DP_M2C_N4...

Page 40: ...4V PCML K19 FMCA_DP_M2C_P15 AN7 1 4V PCML C34 FMCA_GA0 BJ20 Adjustable D35 FMCA_GA1 BJ19 Adjustable D5 FMCA_GBTCLK_M2C_N0 AP10 LVDS B21 FMCA_GBTCLK_M2C_N1 AM10 LVDS D4 FMCA_GBTCLK_M2C_P0 AP9 LVDS B20...

Page 41: ...5 FMCA_LA_RX_P4 AP15 LVDS C18 FMCA_LA_RX_P5 BB19 LVDS G18 FMCA_LA_RX_P6 AR17 LVDS C22 FMCA_LA_RX_P7 BE19 LVDS G21 FMCA_LA_RX_P8 AT15 LVDS G24 FMCA_LA_RX_P9 AR14 LVDS G27 FMCA_LA_RX_P10 AU15 LVDS C26 F...

Page 42: ...DS D14 FMCA_LA_TX_P4 AW19 LVDS H16 FMCA_LA_TX_P5 AY11 LVDS D17 FMCA_LA_TX_P6 BC18 LVDS H19 FMCA_LA_TX_P7 BA12 LVDS D20 FMCA_LA_TX_P8 BE18 LVDS H22 FMCA_LA_TX_P9 BA10 LVDS H25 FMCA_LA_TX_P10 BC12 LVDS...

Page 43: ...W42 1 4V PCML QSFP receiver data 15 QSFP1_RX_N2 AB44 1 4V PCML QSFP receiver data 24 QSFP1_RX_N3 AD44 1 4V PCML QSFP receiver data 17 QSFP1_RX_P0 AC43 1 4V PCML QSFP receiver data 22 QSFP1_RX_P1 W43...

Page 44: ...ix 10 FPGA U1 USB_SCL SDA QSFP28 U17 QSFP_SCL SDA Level Shift QSFP_3p3V_SCL SDA FMCA J13 FMCA_SCL SDA Level Shift FMCA_3p3V_SCL SDA USB PHY U26 FX2_SCL SDA LED Board I2C_SCL SDA Si5341A Clock U7 ADDR...

Page 45: ...Description QSFP_SCL BJ26 1 8V Dedicated I2C to QSFP module QSFP_SDA BH27 1 8V Dedicated I2C to QSFP module Table 25 Stratix 10 FPGA I2C Signals to FMC Connector Schematic Signal Name Stratix 10 FPGA...

Page 46: ...Control signals are allowed for SD and HD modes selections as well as device enable The device can be clocked by the 148 5 MHz voltage controlled crystal oscillator VCXO and matched to incoming signa...

Page 47: ...Names and Functions Board Reference Schematic Signal Name FPGA Pin Number I O Standard U21 10 MF0_BYPASS BA40 1 8V U21 19 MF1_AUTO_SLEEP BA39 1 8V U21 21 MF2_MUTE BB39 1 8V U21 22 MF3_XSD U21 6 MODE_S...

Page 48: ...A U1 OSC_CLK_1 Configuration Clock FPGA_OSC_CLK1 125 MHz LVCMOS CLK_FPGA_50M 50 MHz LVCMOS MAXV_OSC_CLK1 125 MHz PCIE_OB_REFCLK 100 MHz Table 31 On Board Oscillators Source Schematic Signal Name Frequ...

Page 49: ...148 5 MHz LVDS P41 SDI reference clocks REFCLK_SDI_N LVDS P40 4 7 2 Off Board Clock I O The development board has input and output clocks which can be driven onto the board The output clocks can be pr...

Page 50: ...192 0x0570 0000 0x05EF FFFF User hardware1 44032 0x02C0 0000 0x056F FFFF Factory hardware 44032 0x0010 0000 0x02BF FFFF PFL option bits 256 0x000C 0000 0x000F FFFF Board information 256 0x0008 0000 0x...

Page 51: ...s bus C4 FLASH_ADDR12 AT29 1 8V Address bus A5 FLASH_ADDR13 BA30 1 8V Address bus B5 FLASH_ADDR14 BA31 1 8V Address bus C5 FLASH_ADDR15 BB29 1 8V Address bus D7 FLASH_ADDR16 BB30 1 8V Address bus D8 F...

Page 52: ...is on and no other applications that use the JTAG chain are running The design running in the FPGA does not drive the FM bus Execute the steps below to program the Flash 1 Start the Quartus Progammer...

Page 53: ...ses other JTAG based applications such as the Board Test System and the Power Monitor to lose their connection to the board Restart those applications after programming is complete 4 Board Components...

Page 54: ...66 FMC Loopback 10000 5000 4 9 1 External Memory Interface 4 9 1 1 DDR3L The DDR3Lx72 SDRAM DDR3 Low voltage Figure 11 DDR3 Block Diagram VDD VDDQ EMIF H I L O Connector DDR3L x 72 DDR3 SDRAM U1 DDR3...

Page 55: ...Byte 6 7 Byte 4 5 Byte 2 3 Byte 0 1 DQ DQS DM Addr Ctrl clk 4 9 1 3 RLDRAM3 The RLDRAM3 x36 reduced latency DRAM controller is designed for use in applications requiring high memory throughput high c...

Page 56: ...DRIV_ODT_LKB0 1_L QDRIV_ODT_LDA B_L QDRIV_ODT_CK QDRIV_ODT_CK_L QDRIV_ODT_QVLDA0 QDRIV_ODT_QVLDA1 QDRIV_ODT_QVLDB0 QDRIV_ODT_QVLDB1 QDRIV_ODT_ANIV QDRIV_ODT_ANIV 4 9 1 5 FMC Loopback Card The Intel St...

Page 57: ...P_C2M_ P0 GND FMCA_D P_M2C_ P1 3 GND NC GND FMCA_C LK_M2C _N1 GND NC GND FMCA_D P_C2M_ N0 GND FMCA_D P_M2C_ N1 4 FMCA_D P_M2C_ P10 GND FMCA_C LK_M2C _P0 GND NC GND FMCA_G BTCLK_ M2C_P0 GND FMCA_D P_M2...

Page 58: ...C FMCA_L A_TX_N 4 FMCA_L A_RX_P 3 GND FMCA_D P_M2C_ P4 16 FMCA_D P_M2C_ P14 GND FMCA_L A_TX_P 5 FMCA_L A_RX_N 4 NC NC GND GND FMCA_D P_M2C_ P6 GND 17 FMCA_D P_M2C_ N14 GND FMCA_L A_TX_N 5 GND NC GND F...

Page 59: ...M_ P13 GND FMCA_L A_TX_P 14 FMCA_L A_RX_N 12 NC NC FMCA_J TAG_TD O FMCA_3 P3V_SD A GND FMCA_D P_C2M_ N3 32 FMCA_D P_C2M_ N13 GND FMCA_L A_RX_N 14 GND NC GND 3 3V GND FMCA_D P_C2M_ P7 GND 33 GND NC GND...

Page 60: ...or High Pin Count HPC The High Pin Count FMC connections are assigned to columns G and H in the FMCA connector as shown The HPC signaling follows the Vita57 1 standard Low Pin Count LPC The Low Pin Co...

Page 61: ...board J26 and J27 The PCIe slot together with the two auxiliary PCIe power cords are required to power the entire board If you do not connect the 2x4 or 2x3 auxiliary power connections it will prevent...

Page 62: ...pply will provide the entire power to the board without the need to obtain power from the PCIe slot or the 2x4 power connector J26 The power switch SW7 controls powering the board on off 5 2 Power Dis...

Page 63: ...T_GXB S10_VCCPT S10_VCCIO_FMA S10_VCCIO_HILO VCCIO3V VCCPFUSE_SDM 2 5V_DAC 5V_DAC MAX20_VCCONE 12V_G2 EN_12V_G1 EN_3 3V_REG EN_S10_VCC EN_S10_VCCRAM EN_S10_VCCR EN_S10_VCCT EN_1 8V EN_S10_VCCIO_FMCA E...

Page 64: ...the meantime a dedicated FPGA TSD real time monitor solution under ip onchip_sensors is added to each transceiver or EMIF example design to monitor the temperatures of both FPGA core and each transce...

Page 65: ...ry configuration Figure 17 BTS GUI UG 20046 2018 07 20 Intel Corporation All rights reserved Intel the Intel logo Altera Arria Cyclone Enpirion MAX Nios Quartus and Stratix words and logos are tradema...

Page 66: ...ore you use the BTS The BTS relies on the Intel Quartus Prime software s specific library Before running the BTS open the Intel Quartus Prime software to automatically set the environment variable QUA...

Page 67: ...the board powered on when running the demonstration application The BTS cannot run correctly unless the USB cable is attached and the board is on To run the BTS 1 Navigate to the package dir examples...

Page 68: ...ime if open The design begins running in the FPGA The corresponding GUI application tabs that interface with the design are now enabled If you use the Intel Quartus Prime Programmer for configuration...

Page 69: ...he board MAC Indicates MAC Address of the board System MAX Control MAX Ver Indicates the vesion of MAX V code currently running on the board The MAX V code resides in the package dir examples max5 dir...

Page 70: ...o determine the page of flash memory to use for FPGA reconfiguration JTAG Chain The JTAG chain shows all the devices currently in the JTAG chain Note When set to 1 switch SW6 2 MAX BYPASS includes the...

Page 71: ...current state of the board user push buttons Press a push button on the board to see the graphical display change accordingly Platform Designer Standard Memory Map The Platform Designer Standard memo...

Page 72: ...e the flash memory contents change values in the table and click Write The application writes the new values to flash memory and then reads the values back to guarantee that the graphical display accu...

Page 73: ...on the Flash tab Erase Erases flash memory Flash Memory Map Displays the flash memory map for the development board 6 3 5 The XCVR Tab This tab allows you to perform loopback tests on the QSFP and SD...

Page 74: ...eiver VOD Specifies the voltage output differential of the transmitter buffer Pre emphasis tap 1st pre Specifies the amount of pre emphasis on the pre tap of the transmitter buffer 2nd pre Specifies t...

Page 75: ...ber of data errors detected in the hardware Inserted errors Displays the number of errors inserted into the transmit data stream Insert Inserts a one word error into the transmit data stream each time...

Page 76: ...oscilloscope to measure an eye diagram of the PCIe transmit signals Figure 24 The PCIe Tab The following sections describe the controls on the PCIe tab Status Displays the following status informatio...

Page 77: ...of the data sequence is detected Details Shows the PLL lock and pattern sync status Port PCIe x16 Gen3 PMA Setting Allows you to make changes to the PMA parameters that affect the active transceiver...

Page 78: ...es the amount of pre emphasis on the first post tap of the transmitter buffer 2nd post Specifies the amount of pre emphasis on the second post tap of the transmitter buffer Equalizer Specifies the AC...

Page 79: ...serted errors Displays the number of errors inserted into the transmit data stream Insert error Inserts a one word error into the transmit data stream each time you click the button Insert error is on...

Page 80: ...The following sections describe controls in the FMC tab Status Displays the following status information during a loopback test 6 Board Test System UG 20046 2018 07 20 Intel Stratix 10 GX FPGA Develop...

Page 81: ...PLL lock and pattern sync detailed information per channel Port Allows you to specify the interface to test The following port are available to test XCVR CMOS PMA Settings Allows you to make changes t...

Page 82: ...mitter buffer 1st post Specifies the amount of pre emphasis on the first post tap of the transmitter buffer 2nd post Specifies the amount of pre emphasis on the second post tap of the transmitter buff...

Page 83: ...rted errors Displays the number of errors inserted into the transmit data stream Insert Error Inserts a one word error into the transmit data stream each time you click the button Insert Error is only...

Page 84: ...ars Shows the percentage of maximum theoretical data rate that the requested transactions are able to achieve Write MBps Read MBps and Total MBps Show the number of bytes of data analayzed per second...

Page 85: ...cted errors and Inserted errors counters to zeroes Number of Addresses to Write and Read Determines the number of addresses to use in each iteration of reads and writes 6 3 9 The DDR4 Tab This tab all...

Page 86: ...the transaction stream each time you click the button Insert Error is only enabled during transaction performance analysis Clear Resets the detected error and inserted error counters to zeroes Number...

Page 87: ...detail Select a larger number to zoom out to view the entire range of recorded values Speed Specifies how often to referesh the graph Power Information Displays the root mean square RMS current maxim...

Page 88: ...cillators to any frequency between 0 16 MHz and 710 MHz The Clock Controller application sets the Si5341 programmable oscillators to any frequency between 0 1 MHz and 712 5 MHz The Clock Control commu...

Page 89: ...requencies up to 710 MHz The controls of the clock controller are described below F_vco Displays the generating signal value of the voltage controlled oscillator Registers Display the current frequenc...

Page 90: ...able oscillator frequency for the selected clock to the value in the CLK0 to CLK3 controls for the Si5338 Frequency changes might take several milliseconds to take effect You might see glitches on the...

Page 91: ...operate under the authority of an FCC licenseholder or must secure an experimental authorization under Part 5 of the United States CFR Title 47 Safety Assessment and CE mark requirements have been co...

Page 92: ...d to remove all DC power from the board system The socket outlet must be installed near the equipment and must be readily accessible System Grounding Earthing To avoid shock you must ensure that the p...

Page 93: ...during an electrical storm Risk of Fire To reduce the risk of fire keep all flammable materials a safe distance away from the boards and power supply You must configure the development kit on a flame...

Page 94: ...armful interference to radio communications If this equipment does cause harmful interfence to radio or television reception which can be determined by turning the equipment on and off the user is req...

Page 95: ...in unsorted municipal waste A 2 Compliance and Conformity Statements CE EMI Conformity Caution This development board is delivered conforming to relevant standards mandated by Directive 2004 108 EC B...

Page 96: ...20046 2018 07 20 Intel Corporation All rights reserved Intel the Intel logo Altera Arria Cyclone Enpirion MAX Nios Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsid...

Page 97: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Intel DK SI 1SGX L 0A DK DEV 1SGX L 0A DK DEV 1SGX L A...

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