4.6. Components and Interfaces
This section describes the development board's communication ports and interface
cards relative to the Intel Stratix 10 GX FPGA device.
4.6.1. PCI Express
The Intel Stratix 10 GX FPGA development board is designed to fit entirely into a PC
motherboard with a x16 PCI Express slot that can accommodate a full height, 3-slot
long form factor add-in card. This interface uses the Intel Stratix 10 GX FPGA's PCI
Express hard IP block, saving logic resources for the user logic application. The PCI
Express edge connector has a presence detect feature to allow the motherboard to
determine if a card is installled.
The PCI Express interface supports auto-negotiating channel width from x1 to x4 to x8
to x16 by using Intel's PCIe MegaCore IP. You can also configure this board to a x1,
x4, x8 or x16 interface through a DIP switch that connects the
PRSTn
pins for each
bus width.
The PCI Express edge connector has a connection speed of 2.5 Gbps/lane for a
maximum of 40 Gbps full-duplex (Gen1), 5.0 Gbps/lane for maximum of 80 Gbps full-
duplex (Gen 2), or 8.0 Gbps/lane for a maximum of 128 Gbps full-duplex (Gen3).
The power for the board can be sourced entirely from the PC host when installed into
a PC motherboard with the PC's 2x3 and 2x4 ATX auxiliary power connected to the
12V ATX inputs (J26 and J27) of the Intel Stratix 10 development board. Although the
board can also be powered by a laptop power supply for use on a lab bench, Intel
recommends that you do not power up from both supplies at the same time. Ideal
diode power sharing devices have been designed into this board to prevent damages
or back-current from one supply to the other.
The
PCIE_EDGE_REFCLK_P/N
signal is a 100 MHz differential input that is driven
from the PC motherboard onto this board through the edge connector. This signal
connects directly to a Intel Stratix 10 GX FPGA
REFCLK
input pin pair using DC
coupling. This clock is terminated on the motherboard and therefore, no on-board
termination is required. This clock can have spread-spectrum properties that change
its period between 9.847 ps to 10.203 ps. The I/O standard is High-Speed Current
Steering Logic (HCSL). The JTAG and SMB are optional signals in the PCI Express
TDI
to PCI Express
TDO
and are not used on this board. The SMB signals are wired to the
Intel Stratix 10 GX FPGA but are not required for normal operation.
Table 16.
PCI Express Pin Assignments, Schematic Signal Names and Functions
Receive bus
Schematic Signal
Name
FPGA Pin Number
I/O Standard
Description
A11
PCIE_EDGE_PERSTn
AJ34
3V LVCMOS
Reset
A14
PCIE_EDGE_REFCLK_
N
AK40
LVDS
Motherboard reference
clock
A13
PCIE_EDGE_REFCLK_
P
AK41
LVDS
Motherboard reference
clock
B5
PCIE_EDGE_SMBCLK
AU33
1.8V
SMB clock
B6
PCIE_EDGE_SMBDAT
AV35
1.8V
SMB data
continued...
4. Board Components
UG-20046 | 2018.07.20
Intel
®
Stratix
®
10 GX FPGA Development Kit User Guide
29
