Table 39.
MAX V Registers
MAX V Register Values
Description
Configure
Resets the system and reloads the FPGA with a design from the flash memory
based on other MAX V register values.
PSO
Sets the MAX V PSO register.
PSR
Sets the MAX V PSR register. Allows PSR to determine the page of flash memory
to use for FPGA reconfiguration. The numerical values in the list corresponds to
the page of flash memory to load during the FPGA configuration.
PSS
Displays the MAX V PSS register value. Allows the PSS to determine the page of
flash memory to use for FPGA reconfiguration.
JTAG Chain
The JTAG chain shows all the devices currently in the JTAG chain.
Note:
When set to 1, switch SW6.2 (
MAX BYPASS
) includes the MAX V DEVICE in the JTAG
chain. When set to 0, the MAX V device is removed from the JTAG chain. System MAX
and FPGA should all be present in the JTAG chain when running BTS GUI.
6.3.3. The GPIO Tab
The GPIO tab allows you to interact with all the general purpose user I/O components
on your board. You can read DIP switch settings, turn LEDs on or off and detect push
button presses.
Figure 21.
The GPIO Tab
6. Board Test System
UG-20046 | 2018.07.20
Intel
®
Stratix
®
10 GX FPGA Development Kit User Guide
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