Table 10.
Stratix 10 GX FPGA Development Board Components
Board Reference
Type
Description
Featured Devices
U1
FPGA
Stratix 10 GX FPGA, 1SG280LU3F50E3VGS1.
• Adaptive logic modules (ALMs): 933,120
• LEs (K): 2,753
• Registers: 3,732,480
• M20K memory blocks: 11,721
• Transceiver Count: 96
• Package Type: 2397 BGA
U11
CPLD
MAX V CPLD, 2210 LEs, 256 FBGA, 1.8V
VCCINT
.
Configuration and Setup Elements
CN1
On-board Intel FPGA Download
Cable II
Micro-USB 2.0 connector for programming and debugging
the FPGA.
SW2
PCI Express* Control DIP Switch
Enables PCI Express link widths x1, x4, x8 and x16.
SW6
JTAG Bypass DIP Switch
Enables and disbales devices in the JTAG chain. This switch
is located on the back of the board.
SW1
MSEL
Configuration DIP Switch
Sets the Intel Stratix 10
MSEL
pins.
SW3
Board settings DIP Switch
Controls the MAX V CPLD System Controller functions such
as clock reset, clock enable, factory or user design load
from flash and FACTORY signal command sent at power
up. This switch is located at the bottom of the board.
S4
CPU reset push button
The default reset for the FPGA logic. This button resides on
the LED daughter board.
S2
Image select push button
Toggles the configuration LEDs which selects the program
image that loads from flash memory to the FPGA. This
button resides on the LED daughter board.
S1
Program configuration push button
Configures the FPGA from flash memory image based on
the program LEDs. This button resides on the LED
daughter board.
S3
MAX V reset push button
The default reset for the MAX V CPLD System Controller.
This button resides on the LED daughter board.
Status Elements
D14, D16
JTAG LEDs
Indicates the transmit or receive activity of the System
Console USB interface. The TX and RX LEDs would flicker if
the link is in use and active. The LEDs are either off when
not in use or on when in use but idle. These LEDs reside on
the LED daughter board.
D18, D21
System Console LEDs
Indicates the transmit or receive activity of the System
Console USB interface. The TX and RX LEDs would flicker if
the link is in use and active. The LEDs are either off when
not in use or on when in use but idle.
D1, D2, D5
Program LEDs
Illuminates to show the LED sequence that determines
which flash memory image loads to the FPGA when you
press the program load push button. The LEDs reside on
the LED daughter card.
D8
Configuration Done LED
Illuminates when the FPGA is configured. This LED resides
on the LED daughter board.
D6
Load LED
Illuminates during FPGA configuration. This LED resides on
the LED daughter board.
continued...
4. Board Components
UG-20046 | 2018.07.20
Intel
®
Stratix
®
10 GX FPGA Development Kit User Guide
15
