Altera Arria 10 FPGA User Manual Download Page 98

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Figure 5-4: Power Distribution System Block Diagram

12V

DC_INPUT

J13

LTC4357

U55

LTC4357

U54

ISL6115

U56

12V_MAIN

EN_12V

12V_PCIE

J22

LT4357

U50

12V_ATX

12V_OUT

LTC4352

D43

3.3V_PCIE

J22

ET4040

U82, U83

LTC4352

D42

LTC4365-1

U52

12V

A10_VCC_LOW
A10GX VCC, VCCP, VCCHIP,

VCCHSSI

A10_VCCRAM

A10GX VCCRAM

A10_VCCRT_GXB

A10GX VCCRT_GXB(L,R)

EC7401

Multiphase

controller

U34

ET4040

U3, U18,

U30, U11

EN63A0

U10

ET4040

U33,

U90

EN63A0

U31

EN6360

U24

EN6347

U20

EN6347

U23

EN6360

1.1V

16.67A

1.8V

10.23

1.5V
4.7A

0.95V

105.06A

12V

0.95

5.12A

A10_1.8V

A10GX VCCA_PLL, VCCH_GXB(L,R)

A10_VCCPT
A10GX VCCBAT

BEAD

3.13A

A10_VCCIO_MEM

A10GX VCCIO_EMI

MEM_VDDQ
EMI_VDDQ

BEAD

1.5A

1.5V
3.5A

A10_VCCIO_FMCA

A10GX VCCIO (FMCA)

FMCA_VADJ
FMCA VADJ

1.5A

1.5V
3.5A

A10_VCCIO_FMCB

A10GX VCCIO (FMCB)

FMCB_VADJ
FMCB VADJ

1.5A

1.5V
4.5A

MEM_VDD
EMI VDD

3.3V
FMCA, FMCB, CLK cleaner,
EZ-USB, DP, SFP+, QSFP,
SDI, level translator

10.87A

LT3082

U36

5.0V
Char LCD, MAX3378, ADC,
EC7401

5.0V

0.07A

12V
FMCA, FMCB, FAN

EN6337

U57

A10_VCCIO_1.8V
A10GX VCCIO, VCCPGM

EN6337

U51

2.5V

2.31A

1.8V
EPM2210, EPM570, EPCL,
Flash, Oscillators, Level
shifters VADJ

2.5V
MEMVEXT, ENET VDD,
EPM2210, VCCIO1, EMP570,
VCCINT, Oscillators

1.5A

1.8V

2.08A

3.3V

1.26A

3.3V

1.94A

LTC3025

U25

ENET_DVDD

1.0V

0.21A

EN_POWER_SEQ

3.3V_LDO

LT1965

U84

3.3V_MUX

3.3V

3.3V_LDO 1.8V_LDO

R408

.00025

R811

.003

R823

.00025

R850

.00025

R879

.003

R862

.003

R871

.003

R95

.003

12V

3.3V

3.3V_LDO

1.8V_LDO

ENET_DVDD

1.8V_LDO

EN_POWER_SEQ

LTC4365-1

U87

EN_3.3V_LDO

LT1965

U19

5V_SEQ

LTM2977

U81

5V_SEQ

EN1

EN2

EN3

EN4

EN5

EN6

EN7

EN8

EN_3.3V_LDO

EN_1.8V_LDO

EN_POWER_SEQ

CNTL0

CNTL1

POWER_EN

(On Switch)

LT_PGM_HEADER

EN_A10_VCC

EN_A10_GROUP2

EN_A10_1.8V

EN_A10_VCCIO

EN_A10_VCC

EN_A10_GROUP2

EN_A10_1.8V

EN_A10_VCCIO

12V

EN12V

Power UP Sequencing:
1) EN_3.3V_LDO
2) EN_1.8V_LDO
3) EN_12V
4) EN_POWER_SEQ
5) EN_A10_VCC
6) EN_A10_GROUP2
7) EN_A10_1.8V
8) EN_A10_VCCIO

Power DOWN Sequencing:
1) DISABLE A10_VCCIO
2) DISABLE A10_1.8V
3) DISABLE A10_GROUP2
4) DISABLE A10_VCC
5) DISABLE POWER_SEQ
6) DISABLE 12V
7) DISABLE 1.8V_LDO
8) DISABLE 3.3V_LDO

PCIe Component Height Restrictions:
-Top Side (Max): 14.47mm
-Bottom Side (Max) 2.67mm

3.3V_LDO

1.8V_LDO

12V

3.3V

A10_VCC

A10_VCCR

A10_VCCPT

A10_VCCIO_1.8V

IN1

IN2

IN3

IN4

IN5

IN6

IN7

IN8

U13

U27

U22

U17

U35
U88

U39

12V

2.09A

U86

3.3V_PCIE_MUX

1.63A

1.69A

6.20A

2.37A

1.77A

2.27A

3.20A

30.08A

9.24A

11.05A

12V

3.3V_LDO

1.8V_LDO

2.12A

13.05A

R316

.003

R165

.00025

3.3V_OUT

1.8V_LDO

LT1965

U85

EN_1.8V_LDO

Power Measurement

There are 8 power supply rails that have on-board voltage, current, and wattage sense capabilities using

24-bit differential ADC devices. Precision sense resistors split the ADC devices and rails from the primary

supply plane for the ADC to measure voltage and current. A SPI bus connects these ADC devices to the

MAX V CPLD EPM2210 System Controller as well as the Arria 10 GX FPGA.

Daughtercards

The Arria 10 development kit provides a full-featured hardware development platform for prototyping

and testing high-speed serial interfaces to an Arria 10 GX FPGA.

5-52

Power Measurement

UG-01170

2015.06.26

Altera Corporation

Board Components

Send Feedback

Summary of Contents for Arria 10 FPGA

Page 1: ...Arria 10 FPGA Development Kit User Guide Subscribe Send Feedback UG 01170 2015 06 26 101 Innovation Drive San Jose CA 95134 www altera com...

Page 2: ...System 4 1 Preparing the Board 4 2 Running the Board Test System 4 2 Using the Board Test System 4 4 Using the Configure Menu 4 4 The System Info Tab 4 5 The GPIO Tab 4 7 The Flash Tab 4 9 The XCVR T...

Page 3: ...25 10 100 1000 Ethernet PHY 5 28 HiLo External Memory Interface 5 29 FMC 5 36 QSFP 5 43 SFP 5 45 I2C 5 45 Memory 5 48 Flash 5 48 Board Power Supply 5 51 Power Distribution System 5 51 Power Measuremen...

Page 4: ...ce marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance...

Page 5: ...USB BlasterTM II USB Interface FMC Altera LPC x69 CLKIN x8 REFCLK x2 XCVR x16 x66 x1 PCML SMA XCVR OUT x1 SMA CLK OUT QSFP x23 SFP x12 Display Port TX x15 Arria 10 GX FPGA MAX II Related Information...

Page 6: ...observe static discharge precautions Caution Without proper anti static handling the board can be damaged Therefore use anti static handling precautions when touching the board UG 01170 2015 06 26 Han...

Page 7: ...se steps 1 Log on at the myAltera Account Sign In web page and click Sign In 2 On the myAltera Home web page click the Self Service Licensing Center link 3 Locate the serial number printed on the side...

Page 8: ...Kit installer 3 Follow the on screen instructions to complete the installation process Be sure that the installation directory you choose is in the same relative location to the Quartus II software i...

Page 9: ...install the On Board USB Blaster II driver on the host computer Installation instructions for the On Board USB Blaster II driver for your operating system are available on the Altera website On the A...

Page 10: ...h memory and configures the FPGA When the configuration is complete green LEDs illuminate signaling the device configured successfully If the configuration fails the red LED illuminates 2015 Altera Co...

Page 11: ...ve jumpers shunts while the development board is powered on Figure 3 1 Default Switch and Jumper Settings on the Top FMCB FMCA SW3 PRSNTn ON 1 2 3 4 X1 X4 X8 FMCB VCCIO 1 8V 1 5V 1 35V FMCA J11 J8 Not...

Page 12: ...for PCIe x8 ON 4 OFF for 1 35 V MEM_VDD power rail OFF 2 If all of the jumper blocks are open the FMCA and FMCB VCCIO value is 1 2 V To change that value add shunts as shown in the following table Tab...

Page 13: ...m Switch Board Label Function Default Position 1 MSEL0 ON for MSEL0 1 for FPP standard mode OFF 2 MSEL1 ON for MSEL1 0 for FPP standard mode ON 3 MSEL2 ON for MSEL2 0 for FPP standard mode ON 4 VIDEN...

Page 14: ...from flash OFF to load factory from flash OFF 5 RZQ_B2K ON for setting RZQ resistor of Bank 2K to 99 17 ohm OFF for setting RZQ resistor of Bank 2K to 240 ohm OFF UG 01170 2015 06 26 Default Switch a...

Page 15: ...S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com co...

Page 16: ...hardware1 page 1 The development board ships with the CFI flash device preprogrammed with a default Factory FPGA configuration for running the Board Update Portal design example User configuration fo...

Page 17: ...TS open the Quartus II software It sets the environment variable QUARTUS_ROOTDIR automatically The Board Test System uses this environment variable to locate the Quartus II library UG 01170 2015 06 26...

Page 18: ...1 On the Configure menu click the configure command that corresponds to the functionality you wish to test 2 In the dialog box that appears click Configure to download the corresponding design to the...

Page 19: ...tem Info Tab Controls Description Board Information Controls The board information is updated once the GPIO design is configured Otherwise this control displays the default static information about yo...

Page 20: ...ly System Reset SRST Write only Click to reset the FPGA Page Select Override PSO Read Write Page Select Register PSR Read Write Page Select Switch PSS Read only MAX Ver Indicates the version of MAX V...

Page 21: ...rings on the character LCD on your board Type text in the text boxes and then click Display User DIP Switch Displays the current positions of the switches in the user DIP switch bank SW2 Change the sw...

Page 22: ...ntrol displays the current state of the board user push buttons Press a push button on the board to see the graphical display change accordingly 4 8 The GPIO Tab UG 01170 2015 06 26 Altera Corporation...

Page 23: ...Read Values starting at the specified address appear in the table Write Writes the flash memory on your board To update the flash memory contents change values in the table and click Write The applica...

Page 24: ...rn test to flash memory limited to the 512 K test system scratch page Reset Executes the flash device s reset command and updates the memory table displayed on the Flash tab Erase Erases flash memory...

Page 25: ...XCVR Tab This tab allows you to perform loopback tests on the QSFP SFP SMA and SDI ports Figure 4 6 The XCVR Tab UG 01170 2015 06 26 The XCVR Tab 4 11 Board Test System Altera Corporation Send Feedba...

Page 26: ...ettings are available for analysis Serial Loopback Routes signals between the transmitter and the receiver VOD Specifies the voltage output differential of the transmitter buffer Pre emphasis tap 1st...

Page 27: ...the number of data errors detected in the hardware Inserted errors Displays the number of errors inserted into the transmit data stream Insert Error Inserts a one word error into the transmit data str...

Page 28: ...oopback test on your board You can also load the design and use an oscilloscope to measure an eye diagram of the PCIe transmit signals Figure 4 7 The PCIe Tab 4 14 The PCIe Tab UG 01170 2015 06 26 Alt...

Page 29: ...Routes signals between the transmitter and the receiver VOD Specifies the voltage output differential of the transmitter buffer Pre emphasis tap 1st pre Specifies the amount of pre emphasis on the pre...

Page 30: ...the number of data errors detected in the hardware Inserted errors Displays the number of errors inserted into the transmit data stream Insert Error Inserts a one word error into the transmit data str...

Page 31: ...The FMC A Tab This tab allows you to perform loopback tests on the FMC A port Figure 4 8 The FMC A Tab UG 01170 2015 06 26 The FMC A Tab 4 17 Board Test System Altera Corporation Send Feedback...

Page 32: ...e available for analysis Serial Loopback Routes signals between the transmitter and the receiver VOD Specifies the voltage output differential of the transmitter buffer Pre emphasis tap 1st pre Specif...

Page 33: ...he number of data errors detected in the hardware Inserted errors Displays the number of errors inserted into the transmit data stream Insert Error Inserts a one word error into the transmit data stre...

Page 34: ...The FMC B Tab This tab allows you to perform loopback tests on the FMC B port Figure 4 9 The FMC B Tab 4 20 The FMC B Tab UG 01170 2015 06 26 Altera Corporation Board Test System Send Feedback...

Page 35: ...e available for analysis Serial Loopback Routes signals between the transmitter and the receiver VOD Specifies the voltage output differential of the transmitter buffer Pre emphasis tap 1st pre Specif...

Page 36: ...he number of data errors detected in the hardware Inserted errors Displays the number of errors inserted into the transmit data stream Insert Error Inserts a one word error into the transmit data stre...

Page 37: ...ry on your board Figure 4 10 The DDR3 Tab Control Description Start Initiates DDR3 memory transaction performance analysis Stop Terminates transaction performance analysis UG 01170 2015 06 26 The DDR3...

Page 38: ...dwidth of 136512 Mbps or 17064 MBps Error Control This control displays data errors detected during analysis and allows you to insert errors Detected errors Displays the number of data errors detected...

Page 39: ...ry on your board Figure 4 11 The DDR4 Tab Control Description Start Initiates DDR4 memory transaction performance analysis Stop Terminates transaction performance analysis UG 01170 2015 06 26 The DDR4...

Page 40: ...dwidth of 136512 Mbps or 17064 MBps Error Control This control displays data errors detected during analysis and allows you to insert errors Detected errors Displays the number of data errors detected...

Page 41: ...n the Board Test System application You can also run the Power Monitor as a stand alone application The PowerMonitor 32 bit exe and PowerMonitor 64 bit exe reside in the install dir kits device name e...

Page 42: ...the graph Power Information Displays root mean square RMS current maximum and minimum numerical power readings in mA Graph Displays the mA power consumption of your board over time The green line ind...

Page 43: ...cription Serial Port Registers Shows the current values from the Si570 registers for frequency configuration Target frequency MHZ Allows you to specify the frequency of the clock Legal values are betw...

Page 44: ...ight take several milliseconds to take effect You might see glitches on the clock during this time Altera recommends resetting the FPGA logic after changing frequencies Each Si5338 tab for U26 and U14...

Page 45: ...efault Sets the frequency for the oscillator associated with the active tab back to its default value This can also be accomplished by power cycling the board Set New Freq Sets the programmable oscill...

Page 46: ...ol Description Import Reg Map Import register map file generated from Silicon Laboratories ClockBuilder Desktop 4 32 The Clock Control UG 01170 2015 06 26 Altera Corporation Board Test System Send Fee...

Page 47: ...fice and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera war...

Page 48: ...ria 10 MSEL pins and VID_EN pin SW6 Board settings DIP switch Controls the MAX V CPLD System Controller functions such as clock select clock enable factory or user design load from flash and FACTORY s...

Page 49: ...ell as transmit or receive activity D33 SDI Cable LED Illuminates to show the transmit or receive activity D34 D35 D36 D37 D38 PCI Express link LEDs You can configure these LEDs to display the PCI Exp...

Page 50: ...0 is selected S1 S2 S3 General user push buttons Three user push buttons Driven low when pressed D3 D4 D5 D6 D7 D8 D9 D10 User defined LEDs Eight bi color user LEDs Illuminates when driven low Board R...

Page 51: ...b miniature version B SMB connectors that provide a full duplex SDI interface Board Reference Type Description Power Supply J22 PCI Express edge connector Interfaces to a PCI Express root port such as...

Page 52: ...user design at power up FLASH_ADVN N14 1 8 V FSM bus flash memory address valid FLASH_CEN0 D14 1 8 V FSM bus flash memory chip enable FLASH_CEN1 F11 1 8 V FSM bus flash memory chip enable FLASH_CLK N1...

Page 53: ...FM address bus FM_A14 C14 1 8 V FM address bus FM_A15 C15 1 8 V FM address bus FM_A16 H3 1 8 V FM address bus FM_A17 H2 1 8 V FM address bus FM_A18 E13 1 8 V FM address bus FM_A19 F13 1 8 V FM address...

Page 54: ...4 1 8 V FM data bus FM_D11 K13 1 8 V FM data bus FM_D12 L12 1 8 V FM data bus FM_D13 N16 1 8 V FM data bus FM_D14 M13 1 8 V FM data bus FM_D15 L11 1 8 V FM data bus FM_D16 E4 1 8 V FM data bus FM_D17...

Page 55: ...rd FMCB_C2M_PG L5 1 8 V FMC port B power good output FMCB_PRSNTN E2 1 8 V Green LED Illuminates when the FMC port has a board or cable plugged in Driven by the add in card FPGA_CONF_ DONE K1 1 8 V FPG...

Page 56: ...8 V FPGA configuration data FPGA_CONFIG_ D13 P5 1 8 V FPGA configuration data FPGA_CONFIG_ D14 R4 1 8 V FPGA configuration data FPGA_CONFIG_ D15 R5 1 8 V FPGA configuration data FPGA_CONFIG_ D16 M8 1...

Page 57: ...ta FPGA_CONFIG_ D30 R6 1 8 V FPGA configuration data FPGA_CONFIG_ D31 P6 1 8 V FPGA configuration data FPGA_CVP_ CONFDONE M14 1 8 V FPGA Configuration via Protocol CvP done FPGA_DCLK M9 1 8 V FPGA con...

Page 58: ...ble MAX5_WEN R11 1 8 V MAX V Write enable MAX_CONF_ DONE D7 2 5 V On board USB Blaster II configuration done LED MAX_ERROR C7 2 5 V FPGA configuration error LED MAX_LOAD B6 2 5 V FPGA configuration ac...

Page 59: ...nal Detect SENSE_CS0N D9 2 5 V SPI Interface Chip Select SENSE_SCK B9 2 5 V SPI Interface Clock SENSE_SDI B3 2 5 V SPI Interface Serial Data In SENSE_SDO C9 2 5 V SPI Interface Serial Data Out SENSE_S...

Page 60: ...8 V On board USB Blaster II interface reserved for future use USB_CFG9 L3 1 8 V On board USB Blaster II interface reserved for future use USB_CFG10 N1 1 8 V On board USB Blaster II interface reserved...

Page 61: ...ain 3 Click Change File and select the path to the desired sof 4 Turn on the Program Configure option for the added file 5 Click Start to download the selected file to the FPGA Configuration is comple...

Page 62: ...ED2 2 5 V D11 FMCA_PRSNTn 1 8 V D18 FMCB_TX_LED 1 8 V D20 FMCB_RX_LED 1 8 V D21 FMCB_PRSNTn 1 8 V D34 PCIE_LED_X1 1 8 V D35 PCIE_LED_X4 1 8 V D36 PCIE_LED_X8 1 8 V D37 PCIE_LED_G2 1 8 V D38 PCIE_LED_G...

Page 63: ...CPU_RESETn BD27 1 8 V S5 PGM_SEL 2 5 V S6 PGM_CONFIG 2 5 V S7 MAX_RESETn 2 5 V User Defined DIP Switch The Arria 10 GX FPGA development board includes a set of eight pin DIP switch There are no board...

Page 64: ...25 1 8 V D6 USER_LED_G4 J24 1 8 V D5 USER_LED_G5 A19 1 8 V D4 USER_LED_G6 C18 1 8 V D3 USER_LED_G7 D18 1 8 V D10 USER_LED_R0 L27 1 8 V D9 USER_LED_R1 J26 1 8 V D8 USER_LED_R2 K24 1 8 V D7 USER_LED_R3...

Page 65: ...5 8 DisplayPort Schematic Signal Names and Functions Board Reference Schematic Signal Name FPGA Pin Number I O Standard Description 13 DP_3P3V_ CONFIG1 AK31 1 8 V 14 DP_3P3V_ CONFIG2 AK32 1 8 V 18 DP_...

Page 66: ...from 125 Mbps to 11 88 Gbps Control signals are allowed for SD and HD modes selections as well as device enable The device can be clocked by the 148 5 MHz voltage controlled crystal oscillator VCXO an...

Page 67: ...etect or auto mute signal interface Cable Type Data Rate Mbps Maximum Cable Length m Belden 1694A 270 400 Belden 1694A 1485 140 Belden 1694A 2970 120 Table 5 12 SDI Video Input Interface Pin Assignmen...

Page 68: ...ard Reference Schematic Signal Name FPGA Pin Number I O Standard 15 SDO_P SDI_RX_P H40 1 4 V PCML 5 22 SDI Video Input Output Ports UG 01170 2015 06 26 Altera Corporation Board Components Send Feedbac...

Page 69: ..._REFCLK _P N REFCLK _DP _P N REFCLK _SFP _P N REFCLK _QSFP _P N REFCLK _SDI _P N REFCLK _FMCA _P N REFCLK _FMCB _P N REFCLK _SMA _P N CLK _125M_P N Si 5338 CLK 0 CLK 1 CLK 2 CLK 3 CLK _EMI _P N 133 3...

Page 70: ...S R38 REFCLK_SFP_P 644 53125 MHz 1 8 V LVDS AA37 SFP reference clocks REFCLK_SFP_N 1 8 V LVDS AA38 REFCLK_DP_P 270 MHz 1 8 V LVDS AC37 Display port DP reference clocks REFCLK_DP_N 1 8 V LVDS AC38 X1 R...

Page 71: ...bps full duplex Gen1 5 0 Gbps lane for a maximum of 40 Gbps full duplex Gen2 or 8 0 Gbps lane for a maximum of 64 Gbps full duplex Gen3 The power for the board can be sourced entirely from the PC host...

Page 72: ...PRSNT2N_X1 Link with DIP switch B31 PCIE_ PRSNT2N_X4 Link with DIP switch B48 PCIE_ PRSNT2N_X8 Link with DIP switch B15 PCIE_RX_N0 AT39 1 4 V PCML Receive bus B20 PCIE_RX_N1 AP39 1 4 V PCML Receive b...

Page 73: ...PCML Transmit bus A36 PCIE_TX_CN4 AV43 1 4 V PCML Transmit bus A40 PCIE_TX_CN5 AU41 1 4 V PCML Transmit bus A44 PCIE_TX_CN6 AT43 1 4 V PCML Transmit bus A48 PCIE_TX_CN7 AR41 1 4 V PCML Transmit bus A1...

Page 74: ...model RJ45 with internal magnetics that can be used for driving copper lines with Ethernet traffic Table 5 17 Ethernet PHY Pin Assignments Signal Names and Functions Board Reference U15 Schematic Sign...

Page 75: ...n describes the Arria 10 GX FPGA development board s external memory interface support and also their signal names types and connectivity relative to the Arria 10 GX FPGA The HiLo connector supports p...

Page 76: ...DDR_CMD10 H31 1 5 V F4 MEM_ADDR_CMD11 J31 1 5 V G4 MEM_ADDR_CMD12 H34 1 5 V H4 MEM_ADDR_CMD13 H33 1 5 V J4 MEM_ADDR_CMD14 G32 1 5 V K4 MEM_ADDR_CMD15 E32 1 5 V M1 MEM_ADDR_CMD16 F33 1 5 V M2 MEM_ADDR_...

Page 77: ...V2 MEM_CLK_N R31 1 5 V V1 MEM_CLK_P R30 1 5 V B10 MEM_DMA0 E26 1 5 V C4 MEM_DMA1 G27 1 5 V B17 MEM_DMA2 A29 1 5 V F17 MEM_DMA3 F30 1 5 V M16 MEM_DMB0 AB32 1 5 V U16 MEM_DMB1 AG31 1 5 V U11 MEM_DMB2 Y...

Page 78: ...B4 MEM_DQA1 A28 1 5 V B5 MEM_DQA2 A27 1 5 V B6 MEM_DQA3 B27 1 5 V A8 MEM_DQA4 D27 1 5 V B8 MEM_DQA5 E27 1 5 V B9 MEM_DQA6 D26 1 5 V A10 MEM_DQA7 D28 1 5 V B1 MEM_DQA8 G25 1 5 V B2 MEM_DQA9 H25 1 5 V...

Page 79: ...K30 1 5 V D16 MEM_DQA25 H30 1 5 V E16 MEM_DQA26 G30 1 5 V F16 MEM_DQA27 K31 1 5 V D17 MEM_DQA28 H29 1 5 V C18 MEM_DQA29 K29 1 5 V D18 MEM_DQA30 J29 1 5 V E18 MEM_DQA31 F29 1 5 V E2 MEM_DQA32 J28 1 5 V...

Page 80: ...33 1 5 V T18 MEM_DQB15 AH31 1 5 V U15 MEM_DQB16 U31 1 5 V T14 MEM_DQB17 W33 1 5 V U14 MEM_DQB18 W32 1 5 V V14 MEM_DQB19 V31 1 5 V T13 MEM_DQB20 Y34 1 5 V T12 MEM_DQB21 W35 1 5 V U12 MEM_DQB22 W34 1 5...

Page 81: ...QSA_N2 C29 1 5 V G18 MEM_DQSA_N3 L29 1 5 V A6 MEM_DQSA_P0 B26 1 5 V A2 MEM_DQSA_P1 H28 1 5 V A14 MEM_DQSA_P2 C30 1 5 V F18 MEM_DQSA_P3 L30 1 5 V J18 MEM_DQSB_N0 AA32 1 5 V V18 MEM_DQSB_N1 AJ31 1 5 V V...

Page 82: ...oltage of 1 5 V 1 8 V 2 5 V default or 3 3 V The VCCIO supply for the FMC B bank in the HPC provides a variable voltage from 1 2 V to 3 3 V which can be supplied by the FMC module However for device s...

Page 83: ...V PCML K26 FMCA_DP_C2M_N11 AR4 1 4 V PCML K29 FMCA_DP_C2M_N12 AP2 1 4 V PCML K32 FMCA_DP_C2M_N13 AM2 1 4 V PCML K35 FMCA_DP_C2M_N14 AK2 1 4 V PCML K38 FMCA_DP_C2M_N15 AH2 1 4 V PCML C2 FMCA_DP_C2M_P0...

Page 84: ...1 4 V PCML A7 FMCA_DP_M2C_N2 AY6 1 4 V PCML A11 FMCA_DP_M2C_N3 AV6 1 4 V PCML A15 FMCA_DP_M2C_N4 AT6 1 4 V PCML A19 FMCA_DP_M2C_N5 AP6 1 4 V PCML B17 FMCA_DP_M2C_N6 AN4 1 4 V PCML B13 FMCA_DP_M2C_N7 A...

Page 85: ...MCA_DP_M2C_P8 AL3 1 4 V PCML B4 FMCA_DP_M2C_P9 AK5 1 4 V PCML K4 FMCA_DP_M2C_P10 AJ3 1 4 V PCML K7 FMCA_DP_M2C_P11 AH5 1 4 V PCML K10 FMCA_DP_M2C_P12 AG3 1 4 V PCML K13 FMCA_DP_M2C_P13 AF5 1 4 V PCML...

Page 86: ...19 LVDS C11 FMCA_LA_RX_N1 AW14 LVDS G13 FMCA_LA_RX_N2 AN19 LVDS C15 FMCA_LA_RX_N3 AT15 LVDS G16 FMCA_LA_RX_N4 AP16 LVDS C19 FMCA_LA_RX_N5 AV18 LVDS G19 FMCA_LA_RX_N6 AU13 LVDS C23 FMCA_LA_RX_N7 AV21 L...

Page 87: ...MCA_LA_RX_P8 AU8 LVDS G24 FMCA_LA_RX_P9 AW12 LVDS G27 FMCA_LA_RX_P10 AY15 LVDS C26 FMCA_LA_RX_P11 AP21 LVDS G30 FMCA_LA_RX_P12 BA15 LVDS G33 FMCA_LA_RX_P13 BB17 LVDS G36 FMCA_LA_RX_P14 AY17 LVDS H8 FM...

Page 88: ...8 FMCA_LA_TX_N16 AU20 LVDS H7 FMCA_LA_TX_P0 AR22 LVDS H10 FMCA_LA_TX_P1 AN20 LVDS D11 FMCA_LA_TX_P2 AV11 LVDS H13 FMCA_LA_TX_P3 AT17 LVDS D14 FMCA_LA_TX_P4 AW13 LVDS H16 FMCA_LA_TX_P5 AT14 LVDS D17 FM...

Page 89: ...signation For example the pin assignments for FMCA_LA_TX_P1 is J1 H10 and FMCB_LA_TX_P1 is J2 H10 QSFP The Arria 10 GX FPGA development board includes a QSFP module Table 5 20 QSFP Pin Assignments Sch...

Page 90: ...QSFP transmitter data 22 QSFP_RX_P1 P40 1 4 V PCML QSFP transmitter data 14 QSFP_RX_P2 M40 1 4 V PCML QSFP transmitter data 25 QSFP_RX_P3 L42 1 4 V PCML QSFP transmitter data 37 QSFP_TX_N0 K43 1 4 V...

Page 91: ...ct 1 8 SFP_3P3V_RX_LOS AU30 1 8 V Signal present indicator 3 SFP_3P3V_TX_DIS AR35 1 8 V Transmitter disable 2 SFP_3P3V_TX_FLT AT35 1 8 V Transmitter fault 12 SFP_RX_N AA41 1 4 V PCML Receiver data 13...

Page 92: ...andard Description CLOCK_I2C_SCL C12 2 5 V I2C serial clock from MAX V CLOCK_I2C_SDA C10 2 5 V I2C serial data from MAX V Table 5 23 MAV I2C Level Shifter Signals to Arria 10 FPGA Schematic Signal Nam...

Page 93: ...ria 10 I2C serial data to level shifter Table 5 25 Arria 10 I2C Level Shifter to LCD Signals Schematic Signal Name LCD Pin Number I O Standard Description I2C_SCL_DISP 7 5 0 V LCD I2C serial clock fro...

Page 94: ...0930 0000 0x0A0F FFFF Factory software 8 192 0x08b0 0000 0x092F FFFF Zips html web content 8 192 0x0830 0000 0x08AF FFFF User hardware2 44 032 0x0580 0000 0x082F FFFF User hardware1 44 032 0x02D0 0000...

Page 95: ...1 8 V Address bus C2 FM_A7 AN15 1 8 V Address bus A3 FM_A8 AL10 1 8 V Address bus B3 FM_A9 AR10 1 8 V Address bus C3 FM_A10 AP11 1 8 V Address bus D3 FM_A11 AL13 1 8 V Address bus C4 FM_A12 AH11 1 8 V...

Page 96: ...19 1 8 V Data bus G3 FM_D18 BA20 1 8 V Data bus E4 FM_D19 AP24 1 8 V Data bus E5 FM_D20 AP23 1 8 V Data bus G5 FM_D21 BA18 1 8 V Data bus G6 FM_D22 AT24 1 8 V Data bus H7 FM_D23 BD19 1 8 V Data bus E1...

Page 97: ...by the board components An on board multi channel analog to digital converter ADC measures both the voltage and current for several specific board rails The power utilization is displayed on a graphic...

Page 98: ...EQ LTM2977 U81 5V_SEQ EN1 EN2 EN3 EN4 EN5 EN6 EN7 EN8 EN_3 3V_LDO EN_1 8V_LDO EN_POWER_SEQ CNTL0 CNTL1 POWER_EN On Switch LT_PGM_HEADER EN_A10_VCC EN_A10_GROUP2 EN_A10_1 8V EN_A10_VCCIO EN_A10_VCC EN_...

Page 99: ...l Memory Resources DDR3L The DDR3L x 72 SDRAM DDR3 Low Voltage Figure 5 5 DDR3 Block Diagram VDD VDDQ EMIF H I L O Connector DDR3L x 72 DDR3 SDRAM U1 DDR3 SDRAM U2 DDR3 SDRAM U3 DDR3 SDRAM U4 DDR3 SDR...

Page 100: ...4 SDRAM U4 DDR4 SDRAM U5 Byte 8 Byte 6 7 Byte 4 5 Byte 2 3 Byte 0 1 DQ DQS DM Addr Ctrl clk RLDRAM 3 The RLDRAM 3 x 36 reduced latency DRAM controller is designed for use in applications requring high...

Page 101: ...RLDRAM 3 Block Diagram QDR IV QDR IV x 36 SRAM devices enable you to maximize memory bandwidth with separate read and write ports UG 01170 2015 06 26 QDR IV 5 55 Board Components Altera Corporation Se...

Page 102: ...VLDA1 QVLDB0 QVLDB1 DQA0 35 DQB0 35 QDR IV x 36 VDD VREF VDDQ VDD_V1P3 QDRIV_ODT_VREF VDDQ_V1P2 QDRIV_ODT_A0 A24 QDRIV_ODT_DQA0 35 QDRIV_ODT_DQB0 35 QDRIV_ODT_ANIV QDRIV_ODT_CFG_L QDRIV_ODT_RST_L QDRI...

Page 103: ...NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trad...

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