Altera Arria 10 FPGA, User Manual

Page: 57 / 103

Schematic Signal Name Pin Number
I/O Standard Description
FPGA_CONFIG_
D22
R8 1.8 V
FPGA configuration data
FPGA_CONFIG_
D23
T8 1.8 V
FPGA configuration data
FPGA_CONFIG_
D24
P7 1.8 V
FPGA configuration data
FPGA_CONFIG_
D25
R7 1.8 V
FPGA configuration data
FPGA_CONFIG_
D26
R9 1.8 V
FPGA configuration data
FPGA_CONFIG_
D27
T9 1.8 V
FPGA configuration data
FPGA_CONFIG_
D28
T7 1.8 V
FPGA configuration data
FPGA_CONFIG_
D29
P8 1.8 V
FPGA configuration data
FPGA_CONFIG_
D30
R6 1.8 V
FPGA configuration data
FPGA_CONFIG_
D31
P6 1.8 V
FPGA configuration data
FPGA_CVP_
CONFDONE
M14 1.8 V
FPGA Configuration via
Protocol (CvP) done
FPGA_DCLK M9 1.8 V
FPGA configuration clock
FPGA_NCONFIG E14 1.8 V
FPGA configuration active
FPGA_NSTATUS J4 1.8 V
FPGA configuration ready
FPGA_PR_DONE H12 1.8 V
FPGA partial reconfiguration
done
FPGA_PR_ERROR K12 1.8 V
FPGA partial reconfiguration
error
FPGA_PR_READY P12 1.8 V
FPGA partial reconfiguration
ready
FPGA_PR_
REQUEST
T4 1.8 V
FPGA partial reconfiguration
request
UG-01170
2015.06.26
MAX V CPLD System Controller
5-11
Board Components
Altera Corporation
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