Table 5-1: Arria 10 GX FPGA Development Board Components
Board Reference
Type
Description
Featured Devices
U28
FPGA
Arria 10 GX FPGA, 10AX115S2F45I1SG:
• Adaptive logic modules (ALMs): 427,200
• LEs (K): 1,150
• Registers: 1,708,800
• M20K memory blocks: 2,713
• Transceiver count: 96
• Package Type: 1932 BGA
U16
CPLD
MAX V CPLD, 2210 LEs, 256FBGA 1.8V VCCINT
Board Reference
Type
Description
Configuration and Setup Elements
J3
On-Board USB-Blaster II
Micro-USB 2.0 connector for programming and
debugging the FPGA.
SW3
PCI Express Control DIP
switch
Enables PCI Express link widths x1, x4, and x8.
SW4
JTAG Bypass DIP switch
Enables and disables devices in the JTAG chain. This
switch is located on the back of the board.
SW5
FPP Configuration DIP
Switch
Sets the Arria 10
MSEL
pins and
VID_EN
pin.
SW6
Board settings DIP switch
Controls the MAX V CPLD System Controller
functions such as clock select, clock enable, factory or
user design load from flash and FACTORY signal
command sent at power up. This switch is located at
the bottom of the board.
S4
CPU reset push button
The default reset for the FPGA logic.
S5
Image select push button
Toggles the configuration LEDs which selects the
program image that loads from flash memory to the
FPGA.
S6
Program configuration push
button
Configures the FPGA from flash memory image based
on the program LEDs.
S7
MAX V reset push button
The default reset for the MAX V CPLD System
Controller.
Board Reference
Type
Description
Status Elements
D22, D23
JTAG LEDs
Indicates transmit or receive activity of the JTAG
chain. The TX and RX LEDs flicker if the link is in use
and active.
5-2
Board Overview
UG-01170
2015.06.26
Altera Corporation
Board Components
