Altera Arria 10 FPGA, User Manual

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Board Reference
(U15)
Schematic Signal
Name
FPGA Pin
Number
I/O Standard Description
30 ENET_RSET AW23 1.8 V Device reset
75 ENET_RX_N AW24
LVDS
SGMII receive channel
77 ENET_RX_P AV24 SGMII receive channel
81 ENET_TX_N BD23 SGMII transmit channel
82 ENET_TX_P BC23 SGMII transmit channel
55 ENET_XTAL_
25MHZ
—
2.5 V
25-MHz RGMII transmit clock
31 MDI_N0 —
Media dependent interface
34 MDI_N1 —
41 MDI_N2 —
43 MDI_N3 —
29 MDI_P0 —
33 MDI_P1 —
39 MDI_P2 —
42 MDI_P3 —
HiLo External Memory Interface
This section describes the Arria 10 GX FPGA development board’s external memory interface support
and also their signal names, types, and connectivity relative to the Arria 10 GX FPGA.
The HiLo connector supports plugins the following memory interfaces:
• DDR3 x72 (included in the kit)
• DDR4 x72 (included in the kit)
• RLDRAM3 x36 (included in the kit)
• QDR IV x36 (not included. Contact your local Altera sales representative for ordering and availability)
Table 5-18: HiLo EMI Pin Assignments, Schematic Signal Names
Board Reference Schematic Signal Name FPGA Pin Number I/O Standard
F1 MEM_ADDR_CMD0 M32
1.5 V
UG-01170
2015.06.26
HiLo External Memory Interface
5-29
Board Components
Altera Corporation
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