Altera Arria 10 FPGA, User Manual

Page: 67 / 103

Board Reference Schematic Signal Name FPGA Pin Number I/O Standard
1 SDI_TXCAP_N D43 1.4-V PCML
16 SDI_TXCAP_P D44 1.4-V PCML
10 SDI_TXDRV_N — —
11 SDI_TXDRV_P — —
Table 5-11: SDI Cable Equalizer Lengths
The cable equalizer supports operation at 270 Mbit SD, 1.5 Gbit HD, and 3.0, 6.0, and 11.88 Gbit dual-link HD
modes. Control signals are allowed for bypassing or disabling the device, as well as a carrier detect or auto-mute
signal interface.
Cable Type Data Rate (Mbps) Maximum Cable Length (m)
Belden 1694A 270 400
Belden 1694A 1485 140
Belden 1694A 2970 120
Table 5-12: SDI Video Input Interface Pin Assignments, Schematic Signal Names, and Functions
Board Reference Schematic Signal Name FPGA Pin Number I/O Standard
9 AGCN — —
8 AGXP — —
10 MF0_BYPASS AW32 1.8 V
19 MF1_AUTO_SLEEP AY32 1.8 V
21 MF2_MUTE AY35 1.8 V
22 MF3_XSD — —
6 MODE_SEL — —
11 MUTEREF — —
4 SDI_EQIN_N1 — —
3 SDI_EQIN_P1 — —
14 SDO_N / SDI_RX_N H39 1.4-V PCML
UG-01170
2015.06.26
SDI Video Input/Output Ports
5-21
Board Components
Altera Corporation
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