Schematic Signal Name
Pin Number
I/O Standard
Description
PGM_LED0
D6
2.5 V
Flash memory PGM select
indicator 0
PGM_LED1
C6
2.5 V
Flash memory PGM select
indicator 1
PGM_LED2
B7
2.5 V
Flash memory PGM select
indicator 2
PGM_SEL
A7
2.5 V
Toggles the PGM_LED[2:0] LED
sequence
SDI_MF0_BYPASS P13
1.8 V
SDI Interface Mode Select 0 /
Bypass control
SDI_MF1_AUTO_
SLEEP
R14
1.8 V
SDI Interface Mode Select 1 /
Auto Sleep Control
SDI_MF2_MUTE
N12
1.8 V
SDI Interface Mode Select 2 /
Output Mute
SDI_TX_SD_HDN N13
1.8 V
SDI Interface TX Signal Detect
SENSE_CS0N
D9
2.5 V
SPI Interface Chip Select
SENSE_SCK
B9
2.5 V
SPI Interface Clock
SENSE_SDI
B3
2.5 V
SPI Interface Serial Data In
SENSE_SDO
C9
2.5 V
SPI Interface Serial Data Out
SENSE_SMB_CLK A15
2.5 V
I
2
C Interface Clock
SENSE_SMB_
DATA
B13
2.5 V
I
2
C Interface Data
SI516_FS
C5
2.5 V
Silicon Labs SI516 Clock Device
Frequency Select
SI570_EN
A10
2.5 V
Si570 programmable clock
enable
TSENSE_ALERTN B14
2.5 V
MAX1619 device Temperature
Sense Alert Signal
USB_CFG0
M4
1.8 V
On-board USB-Blaster II
interface (reserved for future
use)
USB_CFG1
M3
1.8 V
On-board USB-Blaster II
interface (reserved for future
use)
UG-01170
2015.06.26
MAX V CPLD System Controller
5-13
Board Components
Altera Corporation
