Advanced LAN Bypass, User Manual

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3 Advanced LAN Bypass User Manual
Chapter 1
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1.3 Advanced LAN Bypass Hardware Architecture
Overview
Advanced LAN Bypass may be supported on Ethernet ports hosted either directly on
a motherboard as onboard network ports or via add-in cards such as NMCs or PCIe
NIC cards.
The NICs are connected to the CPU (s) via the PCIe interface.
A dedicated and buffered power rail allows the LAN bypass mechanism to detect sys-
tem events (e.g., power outages or resets) and take the appropriate predefined
action.
Figure 1.1 LAN Bypass Hardware Overview
Two network ports form one bypass segment. The individual segments on the plat-
form are implicitly defined through hardware design (i.e., signal and relay connectiv-
ity).
Bypass control happens on a per-segment basis.
Both network ports of a segment can either connect to their associated NICs, be dis-
connected from their associated NICs, or be switched to bypass mode where both of
the physical LAN ports connect directly to each other, isolating them from their asso-
ciated NICs (see Section 2.3 for more details).
A LAN Bypass MCU controls this connectivity by switching optical or electrical relays
between the ports. Latching relays are used to guarantee that the bypass state or
connectivity is maintained during an absence of power.
Using the Advanced LAN Bypass library and related SW APIs, applications running
on the host system can access the LAN Bypass MCUs in the system in order to
change bypass behavior or to activate and use additional features such as the inte-
grated WDT functionality.
The interface between the host SW and the LAN Bypass MCUs is optimized for low-
latency operation. The LAN Bypass library is designed as a user space library and
communicates directly with the NICs, allowing multiple SW instances to be run in par-
allel.