VSBC-6862
Rev 1.43
66
The VMEA24 Slave window accepts the 'pseudo-RMW' cycles as described on the VME master
chapter.
We also implement a function to have an local exclusive access to the shared memory. This is useful
to keep the memory coherency by avoiding an external VME access between two critical local access.
This function is called 'local_RMW' cycle, and is available through the BSCR[local_rmw] bit.
It has to be used as:
- Activation the 'local-RMW' cycle function
- Make some local cycles, please limit the number of these cycle to a minimum amount
- Deactivation of the 'local-RMW' cycle function
Warning
The 'local-RMW' cycle is not time-limited. If function is not released before the
VME bus timeout, and an external VME master is waiting on this VME slave
Window, it will create an VME bus error. Thus please use the minimum number
of cycles between the activation and the deactivation of this function.
In case of Bus Error, the 'local-RMW' cycle is not automatically deactivated. We
advice that the Software Exception routine include the deactivation of the 'local-
RMW' function.
4.7.5. VME interrupter
The VSBC-6862 can send any interrupt level to the VME bus with its interrupter I(1-7) D08(O) ROAK.
Before generating this interrupt, the interrupt level and the vector must be defined with the VIVEC
register.
The corresponding interrupt signal is activated when writing any value to the VINTER register.
This interrupt stay active until interrupt-handler treats this interrupt. For debug purposes, this interrupt
can be locally deactivated using the SRESR register.
When an interrupt-acknowledge is detected, the vector is returned, and the interrupt is deactivated.
4.7.6. VME interrupt handler
The VSBC-6862 is VME interrupt-handler IH(1-7) D08(O).
This interrupt-handler is able to recognize all IRQ VME levels.
All levels can be masked with the VHM register.
When an IRQ is coming from the VME side, an IRQ1 is sent to the MPC-8260.
The user can then read the IRQ levels active in the VHIL register.
Depending on the IRQ level to be acknowledged, the user can read the vector in the corresponding
offset in the VHV register.
When reading the vector, the interrupt acknowledge cycle is initiated.
4.7.7. VME Mailbox
The VSBC-6862 provides a single Mailbox system. From the VME side, it is composed of a single
register: VSMAIL.
Before using this function, the VSBA24[MailOn] bit must be set to unmask the local IRQ.
When an external master writes to this register, an IRQ6 is sent to the PowerQUICC II.
To clear this IRQ, the PowerQUICC II must write any value to the VSMAIL register.
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