Rev. 1.43
User's
Guide
91
6.3. MPC-8260 internal registers
The MPC-8260 contains some registers to configure for correct operations.
Here follows the specific configuration of these registers for the VSBC-6862:
Internal Memory Map Register:
IMMR
This register set the memory map for the MPC-8260 internal registers.
Bit
Field
Value
Function
0-14 ISB
$XXXY Internal
space base:
user defined
15 Reserved
0 ---
16-23
Partnum
$00
Part number, read only:
$00 = MPC-8260
24-31
Masknum
$xx
Mask number, read only:
mask number
Typical value: IMMR = $XXXX0000
Bus Configuration Register:
BCR
This register configures various features on the PQII, and is mainly already defined by the ResetWord.
Bit
Field
Value
Function
0 EBM
0
External bus mode:
single MPC8260 mode
1-3
APD
0
Address phase delay:
0
4 L2C
0
Secondary cache:
no
5-7
L2D
00
L2 cache hit delay:
0
8
PLDP
0
Pipeline max. depth:
0
9
EAV
0
Enable address visibility:
no
10-11 Reserved
00
---
12
ETM
0
Extended transfer mode:
disabled
13
LETM
0
Local bus extended mode:
disabled
14
EPAR
0 Even
parity:
no
15
LEPAR
0
Local bus even parity: no
16-18
NPQM
0
Non PQII master:
no
19-20 Reserved
00
---
21
EXDD
0
Ext. master delay disable:
no
22-26 Reserved
00000 ---
27
ISPS
0
Int. space port size:
64 bits
28-31 Reserved
0000 ---
Typical value: BCR
= $00000000
60x bus Arbiter Configuration Register:
PPC_ACR
This register defines the arbiter modes and parked master for the 60x bus. These bits are already
defined in the ResetWord.
Bit
Field
Value
Function
0-1 Reserved
00 ---
2
DBGD
0
Data bus grant delay:
DBG asserted with TS
3 EARB
0
External arbitration:
internal
4-7
PRKM
0000
Parking master:
CPM high level
Typical value: PPC_ACR = $00
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