Rev. 1.43
User's
Guide
89
6
Board initialization
The VSBC-6862 must set up the specific hardware organization for the PowerQUICC II processor.
This setup must be completed on software initialization to ensure an adequate operation.
Three steps are needed to initialize the board:
1)
ResetWord configuration
2)
8260 internals registers configuration
3)
8260 internals registers board dependants and board registers configuration
The first step configures the 8260 low level functions like clocks configuration and pins multiplexing.
The ResetWord is loaded by the 8260 from the boot Flash memory bank.
When the ResetWord is invalid in Flash memory, the VSBC-6862 must be started with the ResetConf
jumper plugged-in in order to use the 8260 default ResetWord, and then the ResetWord can be
programmed in the Flash memory through the JTAG port.
The ResetWord is stored in the first addresses in the Flash memory and can be modified like any data
in Flash memory. This step is described below.
The second step configures the main 8260 functions like bus modes.
This is done writing internal registers in the 8260. The base address is defined by the ISB bits in the
ResetWord. This base address can be modified later using the ISB bits in the IMMR register. This step
is described below.
The third step is to configure the VSBC-6862 specific registers for purposes like memory control and
pin multiplexing.
This is done programming registers with the values specified in this manual. These registers are
described above in the corresponding peripherals chapters.
In the following descriptions,
bold
values are to be respected in order to obtain
the board working correctly.
6.1. Clock configuration
The main clock is a 66 MHz crystal controlled oscillator. It is used for the external bus.
The PowerQUICC II uses this external bus frequency to create two internal clocks. One for the CPM
and the other for the core. Internally, two multiplication factors are used to generated these internal
clocks. To define these multiplication factors, two values called MODCK are to be fixed.
The first MODCK[1-3] bits are fixed by defining the levels on the corresponding pins. These pins are
factory defined at 101 or 111 depending on the processor speed mounted.
The next MODCK_H bits are contained in the Reset Word (see below). ACTIS defined these bits at
0101.
It sets the CPM frequency at 133 MHz and the core frequency at 133 or 200 MHz, depending of the
board version.
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