VSBC-6862
Rev 1.43
14
2.3. SRAM memory
1 MBytes of SRAM memory are provided on-board, this memory is controlled with the Chip Select 9.
This memory is shared between the PowerQUICC II and the VME bus.
It is organized in memory width of 32 bits.
A special function is provided for memory saving with the usage of the Stand-By power signal from the
VME bus. When the Board Power is shutdown, the SRAM memory will switch its power lines to the
VME Stand-By power signal.
2.4. Real Time Clock with SRAM memory
The VSBC-6862 includes a real time clock device, with as an additional feature, a battery backed 32
kbyte SRAM. This device is controlled by the Chip Select 3.
Its 32 kbyte SRAM provides flexible user data storage with retention capability by its SNAPHAT
battery pack. This device is connected on an 8 bits wide data path.
This device provides also functions like Alarm, Battery Test, and Watchdog function.
The RTC data are accessible like SRAM Bytes.
This device is also accessible from the VME bus.
Note:
The SNAPHAT housing plugged on the M48T37V contains both battery and crystal.
Thus, for the minimum frequency error, the user has to calibrate the RTC in case of
battery
replacement.
2.5. IP modules
The VSBC-6862 provides four IP module slots, which are compliant with the ANSI/VITA 4-1995.
It provides support for 8 MHz type as well as DMA modules.
The IP interface offers an architecture for I/O extension through inexpensive mezzanine modules for
various categories like:
•
Digital and analog functions
•
Serial communication controllers
•
Network and fieldbus interfaces
This interface gives the possibility to easily customize the VSBC-6862.
This IP bus interface is implemented on the VSBC-6862 through a specific CPLD, which provides the
interface between the PowerQUICC II processor and the four IP module slots.
For overall information, please consult the Appendix: List of main ACTIS IP modules.
A choice of IP modules and transition modules from ACTIS Computer is
available on our web site:
www.actis-computer.com
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