Rev. 1.43
User's
Guide
59
4.6.4. DMA functions
The DMA is controlled by the IDMA channels of the MPC-8260.
The DCR registers set-up the DMA channels configuration, as following:
ENDMA bit:
It enables the DMA request to the PowerQUICC II processor, in accordance
with the S0 bit definition.
After system reset, all DMA request sources are disabled.
When this bit is set, the Transmit Clock line for the serial port 4 is not
accessible.
S0 bit:
It allows selection between both DMA channels (/DREQ[1:0]) present on the
IP
slot.
The DMA channels are controlled by the IDMA channels, with IP Slot A controlled by IDMA1, Slot B
controlled by IDMA2, Slot C controlled by IDMA3
The DMA signals are assigned on the PowerQUICC II as the following table:
MPC-8260
Peripheral function
I/O
Function
I/O
Signal
Description
DMA
PC0
IDMA1: DREQ
I
DMARQ1
IDMA request 1
PC1
IDMA2: DREQ
I
DMARQ2
IDMA request 2
PA0
IDMA3: DREQ
I
DMARQ3
IDMA request 3
PA5
IDMA4: DREQ
I
DMARQ4
IDMA request 4
PD6
IDMA1: DACK
I
DMACK1
IDMA acknowledge 1
PC3
IDMA2: DACK
I
DMACK2
IDMA acknowledge 2
PA2
IDMA3: DACK
I
DMACK3
IDMA acknowledge 3
PA3
IDMA4: DACK
I
DMACK4
IDMA acknowledge 4
PC22
IDMA1: DONE
I/O
DMADONE1
IDMA done 1
PC2
IDMA2: DONE
I/O
DMADONE2
IDMA done 2
PA1
IDMA3: DONE
I/O
DMADONE3
IDMA done 3
PA4
IDMA4: DONE
I/O
DMADONE4
IDMA done 4
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