Rev. 1.43
User's
Guide
45
Typical Option Register:
Bit
Field
Value
Function
0-16
AM
$FFC0 0
Address mask:
for 4 MBytes
17-18
Reserved 00
---
19
BCTLD
0 Buffer
control:
on
20
CSNT
0
Chip select negation time:
normal
21-22
ACS
00
Address to CS setup:
0
23
Reserved 0
---
24-27
SCY
0110
Cycle
length:
6
28
SETA
1
External access termination:
external
29
TRLX
0 Timing
relaxed:
off
30
EHTR
0
Extended hold time:
off
31
Reserved 0
---
->
OR0
= $FFC0 0068
This example is for a 8MByte VSBC-6862. There is two 4MByte Flash memory banks.
This Chip Select is connected to the second bank of Flash memory, depending of the 'BootBnk'
jumper. The GPCM is used to control the Flash memory.
As this chip select controls the same device as CS0, it will have the same register values:
Typical Base Register:
->
BR2
= $zzzz 1801
Typical Option Register:
->
OR2
= $FFC0 0068
Once these Chip Select registers are configured, access to the Flash memory can be done.
The Flash memory recognize the standard JEDEC commands, these commands will be described
below.
4.2.2. FLASH Programming
The device is programmed by executing the program command sequence. This will invoke the
Embedded Program Algorithm, which is an internal algorithm that automatically setup the program
pulse widths and verifies proper cell margin. Each sector can be programmed and verified in less than
0.5 seconds.
The program sequence is the following:
Sequence
Address
Data
1
Base + $555
$AAAA
2
Base + $2AA
$5555
3
Base + $555
$A0A0
4
Address
Data: 16 bits
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