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AR-B1380/AR-1380A User’ s Guide

Page 40

Help to PGF File

This option gives information on how to write a PGF file and how to generate ROM pattern files.
An example PGF is also included.
Move the reverse video bar to <Generate ROM File(s)> then press [ENTER]. The ROM pattern
file is a binary file. The file size will be the same size as the EPROM that you assigned in the
PGF. For example, if you are using 128KX8 EPROM memory chips, then the size of ROM
patterns file will be 131072 bytes. For other chips the file size will be:

64KX8 EPROM----65536 bytes
256KX8 EPROM —262144 bytes
512KX8 EPROM---524288 bytes
1MX8 EPROM -----1048576 bytes

(E) RFGDEMO.PGF

RFGDEMO.PGF This file provides a sample PROGRAM GROUP FILE which illustrates how to create

ROM pattern files correctly.

The PGF is an ASCII text file that can be created by using any text editor, word processor or DOS <COPY
CON> command. The PGF lists what files will be copied and if DOS is going to be copied. This file can
have any DOS filename, but the extension name must be *.PGF. For example, the followings are valid
filenames.

RFGDEMO.PGF
MYRFG.PGF
MSDOS.PGF
….

An examples of the *.PGF file is as follows.

ROM_NAME=TEST1; ROM pattern file name is TEST1
;The output file names will be TEST1.R01, TEST1.R02..etc.
DOS_DRIVE=C:

; DOS system drive unit is drive C:

;If user does not want to copy DOS
;system files onto the ROM disk
;write as DOS_DRIVE=NONE
ROM_SIZE=128

;128 means 128KX8 (27C/29F010) EPROM size used

;256 means 512KX8 (27C/29F020) EPROM size used
;512 means 512KX8 (27C/29F040) EPROM size used
;1024 means 1MX8 (27C080) EPROM size used

The following two files are options which depending on whether you want the ROM disk to be bootable or
not.

CONFIG.SYS
AUTOEXEC.BAT

;Below are user’ s files
A:\USER1.COM ; File USER1.COM on root of drive A:
USER2.EXE ; File USER2.EXE on current directory & drive
C:\TTT\USER3.TXT ; File USER3.TXT on sub-directory TTT of drive C:
Note: Anything appearing after a “ ;” semicolon is considered a text note that does not affect the PGF file, but it is a
good organizational idea to keep these notes for future use.0

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Summary of Contents for AR-B1380

Page 1: ...AR B1380 AR B1380A Half Size All In One 386SX CPU CARD User s Guide Edition 1 1 Book Number AR B1380 00 A02 ...

Page 2: ......

Page 3: ...ard Disk Drive Connector 20 3 3 2 CN2 Floppy Disk Drive Connector 21 3 3 3 CN3 Parallel Port Connector 21 3 3 4 CN6 Ethernet RJ 45 Header 22 3 3 5 CN7 CN8 PC 104 Connector 22 3 3 6 PS 2 Keyboard and Mouse 25 3 3 7 Power Connector 26 3 3 8 J5 External Speaker Header 26 3 3 9 J7 Reset Header 26 3 3 10 Board Battery Configuration 27 3 3 11 JP3 CPU Base Clock Selector 27 3 3 12 Serial Port 29 3 3 13 L...

Page 4: ...nd RAM Disk 59 7 BIOS CONSOLE 60 7 1 BIOS SETUP OVERVIEW 60 7 2 STANDARD CMOS SETUP 61 7 3 ADVANCED CMOS SETUP 62 7 4 ADVANCED CHIPSET SETUP 65 7 5 PERIPHERAL SETUP 67 7 6 PASSWORD SETTING 68 7 6 1 Setting Password 68 7 6 2 Password Checking 69 7 7 LOAD DEFAULT SETTING 69 7 7 1 Auto Configuration with Optimal Setting 69 7 7 2 Auto Configuration with Fail Safe Setting 69 7 8 BIOS EXIT 69 7 8 1 Save...

Page 5: ...BOARD This guide introduces the Acrosser AR B1380 1380A CPU card s functions features and how to start set up and operate your AR B1380 1380A You can also find general system information here 0 3 BEFORE YOU USE THIS GUIDE If you have not already installed this AR B1380 1380A refer to Chapter 3 Setting up the System in this guide Check the packing list make sure all the accessories are included in ...

Page 6: ...5 Software Installation describes the utility diskette solid state disk s write protect function and the watchdog timer l Chapter 6 Solid State Disk describes the various types of SSD s installation methods l Chapter 7 BIOS Console providing the BIOS settings l Chapter 8 Specifications SSD Types Supported l Chapter 9 Using the Memory Banks l Chapter 10 Placement Dimensions l Chapter 11 Programming...

Page 7: ...execute normally For diskless application the AR B1380 AR B1380A provides up to 3 MB of bootable EPROM FLASH or SRAM disk by using 64Kx8 to 1Mx8 memory chips The AR B1380A has VGA and LAN onboard and offers the most exciting possibilities yet to the industry The onboard VGA LCD controller brings about a whole new dimension of industrial computing No longer do you have to worry about adding an extr...

Page 8: ...tructure l ALI M6117C 80386SX 25 33 40 MHz CPU 33 MHz CPU is standard l ISA and non stack through PC 104 extension bus l 2 MB DRAM onboard system with a DRAM socket and SIMM bank for expansion l On board CRT and LCD panel displays available for AR B1380A only l Supports 2 IDE hard disk drive l Supports 8 pin 4pin 2 5mm connector l Supports 2 floppy disk drives with 34 pin 2 54mm connector for 1380...

Page 9: ...er consumption here is almost zero when the clock stops The internal structure of this core is 32 bit and it s address bus with a very low supply current Real mode as well as protected mode are available and can run MS DOS MS Windows OS 2 and UNIX 2 2 DMA CONTROLLER The equivalent of two 8237A DMA controllers are implemented in the AR B1380 AR B1380A CPU board Each controller is a four channel DMA...

Page 10: ...ledgment is received for the previous byte The output buffer full interruption may be used for both send and receive routines 2 4 INTERRUPT CONTROLLER The equivalent of two 8259 Programmable Interrupt Controllers PIC are included on the AR B1380 AR B1380A board They accept requests from the peripherals resolve priorities on pending interrupts in service issue interrupt requests to the CPU and prov...

Page 11: ... 1 1F0 1F8 Fixed disk 0 3 201 Game port 208 20A EMS register 0 218 21A EMS register 1 278 27F Parallel printer port 2 LPT 2 2E8 2EF Serial port 4 COM 4 2F8 2FF Serial port 2 COM 2 3 300 31F Prototype card streaming type adapter 320 33F LAN adapter 378 37F Parallel printer port 1 LPT 1 380 38F SDLC bisynchronous 3A0 3AF Bisynchronous 3B0 3BF Monochrome display and printer port 3 LPT 3 3C0 3CF EGA V...

Page 12: ...8 Input Output B13 IOW Input Output A14 SA17 Input Output B14 IOR Input Output A15 SA16 Input Output B15 DACK3 Output A16 SA15 Input Output B16 DRQ3 Input A17 SA14 Input Output B17 DACK1 Output A18 SA13 Input Output B18 DRQ1 Input A19 SA12 Input Output B19 REFRESH Input Output A20 SA11 Input Output B20 BUSCLK Output A21 SA10 Input Output B21 IRQ7 Input A22 SA9 Input Output B22 IRQ6 Input A23 SA8 I...

Page 13: ...I O Channel Pin Assignments 2 5 REAL TIME CLOCK AND NON VOLATILE RAM The AR B1380 AR B1380A contains a real time clock compartment that maintains the date and time in addition to storing configuration information about the computer system It contains 14 bytes of clock and control registers and 114 bytes of general purpose RAM Because of the use of CMOS technology it consumes very little power and ...

Page 14: ...transmit side and convert serial data to parallel on the receiver side The serial format in order of transmission and reception is a start bit followed by five to eight data bits a parity bit if programmed and one 1 5 five bit format only or two stop bits The ACEs are capable of handling divisors of 1 to 65535 and produce a 16x clock for driving the internal transmitter logic Provisions are also i...

Page 15: ...terrupt Identification Register IIR Bit 0 0 if Interrupt Pending Bit 1 Interrupt ID Bit 0 Bit 2 Interrupt ID Bit 1 Bit 3 Must be 0 Bit 4 Must be 0 Bit 5 Must be 0 Bit 6 Must be 0 Bit 7 Must be 0 5 Line Control Register LCR Bit 0 Word Length Select Bit 0 WLS0 Bit 1 Word Length Select Bit 1 WLS1 WLS1 WLS0 Word Length 0 0 5 Bits 0 1 6 Bits 1 0 7 Bits 1 1 8 Bits Bit 2 Number of Stop Bit STB Bit 3 Pari...

Page 16: ... Line Signal Detect DSLSD Bit 4 Clear to Send CTS Bit 5 Data Set Ready DSR Bit 6 Ring Indicator RI Bit 7 Received Line Signal Detect RSLD 9 Divisor Latch LS MS LS MS Bit 0 Bit 0 Bit 8 Bit 1 Bit 1 Bit 9 Bit 2 Bit 2 Bit 10 Bit 3 Bit 3 Bit 11 Bit 4 Bit 4 Bit 12 Bit 5 Bit 5 Bit 13 Bit 6 Bit 6 Bit 14 Bit 7 Bit 7 Bit 15 Desired Baud Rate Divisor Used to Generate 16x Clock Present Error Difference Betwee...

Page 17: ... 1 2 3 4 5 6 7 0 ERROR SLCT PE ACK BUSY Figure 2 2 Printer Status Buffer NOTE X represents not used Bit 7 This signal may become active during data entry when the printer is off line during printing or when the print head is changing position or in an error state When Bit 7 is active the printer is busy and can not accept data Bit 6 This bit represents the current state of the printer s ACK signal...

Page 18: ...gh speed access applications as controllers for industrial use or line test instruments etc 2 10 ETHERNET CONTROLLER The Ethernet controller of the AR B1380A is a highly integrated design that provides all Media Access Control MAC and Encode Decode ENDEC functions in accordance with the IEEE 802 3 standard The Ethernet controller can interface directly with the PC AT ISA bus without any external d...

Page 19: ...tors locations and the pin assignments CAUTION This CPU board doesn t support double sided SIMM type DRAM It only supports single sided SIMMs Figure 3 1 Jumper Connector Placement ALi M6117C VGA 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 2 2 M1 M2 M3 MEM1 MEM2 MEM3 1 2 3 2 1 1 2 3 1 2 3 A B C A B C C B A A B C 1 2 3 1 1 BUS1 BUS2 CN1 CN2 CN3 CN4 DB2 1 SIMM1 CN9 H1 H2 H3 U15 105 104 1 U17 105 104 1 U7 DB1 CN7...

Page 20: ...oltage selector 33 JP6 3 Pin 1MX8 EPROM selector 52 JP7 3 Pin PS 2 mouse selector 25 JP8 3 Pin battery charger selector 29 JP9 3 Pin RS 485 terminator selector 29 JP10 6 Pin S S D D O C Selector 49 JP11 9 Pin RS 232 RS 485 selector for CN5 29 LED1 Power Watchdog LED 30 M1 M3 Memory type setting 52 SIMM1 DRAM socket for SIMM memory socket 31 SW2 1 SW2 2 Set the base I O port address 49 SW2 3 SW2 4 ...

Page 21: ...N Otherwise the jumper can be left to the side or completely off the block to keep both 1 2 and 2 3 open off We will show the locations of the AR B1380 AR B1380A jumper pins and the factory default settings CAUTION Do not touch any electronic component unless you are safely grounded Wear a grounded wrist strap or touch an exposed metal part of the system unit chassis The static discharges from you...

Page 22: ...ram The following table illustrates the hard disk drive s 40 pin connector pin assignments Figure 3 2 CN1 Hard Disk IDE Connector Pin Signal Pin Signal 1 RESET 2 GROUND 3 DATA 7 4 DATA 8 5 DATA 6 6 DATA 9 7 DATA 5 8 DATA 10 9 DATA 4 10 DATA 11 11 DATA 3 12 DATA 12 13 DATA 2 14 DATA 13 15 DATA 1 16 DATA 14 17 DATA 0 18 DATA 15 19 GROUND 20 VDOM 21 NOT USED 22 GROUND 23 IOW 24 GROUND 25 IOR 26 GROUN...

Page 23: ...TA 6 DRVEN 1 24 WGATE 8 INDEX 26 TRK 0 10 MTR0 28 WRITE PROTECT 12 DRV1 30 READ DATA 14 DRV0 32 HDSEL 16 MTR1 34 DISKCHG Table 3 3 FDD Pin Assignment 3 3 3 CN3 Parallel Port Connector To use the parallel port an adapter cable has connected to the CN3 26 pin header type connector This adapter cable is mounted on a bracket and is included in your AR B1380 AR B1380A package The connector for the para...

Page 24: ...ect 26 PRCG Table 3 4 Parallel Port Pin Assignment 3 3 4 CN6 Ethernet RJ 45 Header The system supports onboard network connectivity To utilize this function install the network driver from the utility diskette and connect the cable to the following RJ 45 header Figure 3 5 CN6 RJ 45 Header J9 RJ45 HEADER Signal J9 RJ45 HEADER Signal 1 TPTX 8 No connection 2 TPTX 9 No connection 3 TPRX 10 No connect...

Page 25: ...nto the falling edge This signal is forced high during DMA cycles IOCHCK Input The I O Channel Check is an active low signal which indicates that a parity error exist on the I O board IOCHRDY Input Open collector This signal lengthens the I O or memory read write cycle and should be held low with a valid address IRQ 3 7 9 12 14 15 Input The Interrupt Request signal indicates I O service request at...

Page 26: ...to indicate a memory refresh cycle and can be driven by the microprocessor on the I O channel TC Output Terminal Count provides a pulse when the terminal count for any DMA channel is reached SBHE Input Output The System Bus High Enable indicates the high byte SD8 SD15 on the data bus MASTER Input The MASTER is the signal from the I O processor which gains control as the master and should be held l...

Page 27: ...PS 2 Keyboard Connector CN9 is a Mini DIN 6 pin connector with support for a PS 2 keyboard This connector is also IBM compatible with the keyboard adapter cable When you use the PS 2 mouse adjust JP7 to 2 3 and connect the adapter cable to CN9 Figure 3 9 CN9 6 Pin Mini Din Keyboard Connector J9 PS 2 Mouse Selector A PC AT compatible mouse can be used by connecting the provided adapter cable betwee...

Page 28: ... Figure 3 3 J3 4 pin Power Connector 3 3 8 J5 External Speaker Header Besides the on board buzzer you can use an external speaker by connecting J5 header directly Figure 3 4 J5 External Speaker Header 3 3 9 J7 Reset Header J7 is used to connect to an external reset switch Shorting these two pins will reset the system Figure 3 5 J7 Reset Header 1 Reset 2 Reset 1 5 VDC 2 GND 3 GND 4 12 VDC 1 GND 2 5...

Page 29: ...able 3 8 JP8 Battery Charger Selector 2 J8 External Battery Connector The J8 allows the users to connector an external 4 5 to 6 VDC battery to the AR B1380 AR B1380A If the on board battery is fully discharged the SRAM disk will draw the battery current The battery charger on AR B1380 AR B1380A doesn t source charge current to the external battery which connects to J8 Figure 3 15 J8 External Batte...

Page 30: ...380 AR 1380A User s Guide Page 28 JP3 CPU Base Clock Setting 1 2 4 6 16 7 MHz 1 2 3 5 25 MHz 1 2 5 6 30 MHz 1 3 5 6 Factory Preset 33 3 MHz 2 4 5 6 37 5 MHz 1 3 2 4 40 MHz Table 3 9 JP1 CPU Base Clock Select ...

Page 31: ...85 connecting with J9 CN5 RS 232 or RS 485 Selector Setting CN5 is RS 485 compatible 1 2 4 5 7 8 CN5 is RS 485 compatible Factory Preset 2 3 5 6 8 9 Table 3 10 JP11 RS 232 RS 485 Select for CN5 2 JP9 RS 485 Terminator Selector RS 485 may need to be terminated when there are multiple blocks on one line JP9 RS 485 Terminator Setting 1 2 Enable 2 3 factory Preset Disable Table 3 11 JP9 RS 485 Termina...

Page 32: ... the AR B1380 AR B1380A COM A uses one on board D type 9 pin male connector DB2 which is located at the top of the card and COM B uses one 10 pin header CN5 Use the BIOS Setup program to configure these two serial ports and adjust the jumpers on JP1 and JP4 CN5 DB2 Signal CN7 DB2 Signal 1 1 DCD 2 6 DSR 3 2 RXD 4 7 RTS 5 3 TXD 6 8 CTS 7 4 DTR 8 9 RI 9 5 GND 10 Not Used Table 3 13 Serial Port Pin As...

Page 33: ...timer LED1 is located at the upper left corner of the board above the SIMM socket 3 3 14 DRAM Configuration There is 2MB DRAM onboard For memory expansion a SOJ socket and 72 pin SIMM socket are provided The SIMM socket supports single sided SIMM modules Single Line Memory Modules which is designed to accommodate 256Kx36 bit to 4Mx36 SIMMs This provides the user with up to 32MB of main memory The ...

Page 34: ...nc 6 AGND 14 Vertical Sync 7 AGND 15 Not Used 8 AGND Table 4 1 CRT Connector Pin Assignments 4 2 LCD FLAT PANEL DISPLAY This section describes the configuration and installation procedure for a LCD display Skip this section if you are using a CRT monitor only AR B1380 doesn t provide the LCD function Use the Flash Memory Writer utility to download the new BIOS file into the ROM chip to configure t...

Page 35: ...n 1 of the cable connector is indicated with a sticker and pin1 of the ribbon cable usually has a different color 4 2 1 Inverter Board Description The inverter board supplies the high voltage signals to drive the LCD panel by converting the 12 volt signal from the AR B1380A into high voltage AC signal for LCD panel It can be installed freely on the space provided over the VR board If the VR board ...

Page 36: ...nal from M or LP JP2 DE M Signal Setting 1 2 Factory Preset DE M 2 3 E LP Table 4 2 JP2 DE E Signal from M or LP Select 2 JP5 LCD Voltage Selector JP5 LCD Voltage Selector Setting 3 5 4 6 Factory Preset 3 3 VDC 1 3 2 4 5 VDC Table 4 3 LCD Voltage Selector ...

Page 37: ... FLM 6 GND 7 P0 8 P1 9 P2 10 P3 11 P4 12 P5 13 GND 14 P6 15 P7 16 P8 17 P9 18 P10 19 P11 20 GND 21 P12 22 P13 23 P14 24 P15 25 P16 26 P17 27 GND 28 P18 29 P19 30 P20 31 P21 32 P22 33 P23 34 GND 35 VLCD 36 VLCD 37 12V 38 12V 39 GND 40 GND 41 DE 42 ENABLK 43 GND 44 ENAVEE Table 4 4 LCD Display Assignments 4 J1 Touch Screen Connector The J1 is a 3 pin JST connector connecting to the touch screen modu...

Page 38: ...0 2 3 NEC NL 6448AC33 10 TFT 10 4 4 HITACHI LMG5371 MONO 9 4 Dual Scan 5 HITACHI LMG9200 DSTN 9 4 6 HITACHI LMG9400 DSTN 10 4 7 ORION OGM 640CN03C S DSTN 10 4 8 SHARP LQ10D321 TFT 10 4 Table 4 5 LCD Panel Type List CAUTION 1 If you want to use LCD panel you must update the AR B1380A s BIOS Please contact Acrosser for the latest BIOS update 2 If you need details to update the BIOS version or use ot...

Page 39: ... 3 Set the jumpers Step 4 Make sure that the power supply connected to your passive CPU board backplane is turned off Step 5 Plug the CPU card into a free AT bus slot or PICMG slot on the backplane and secure it in place with a screw to the system chassis Step 6 Connect all necessary cables Make sure that the FDC HDC serial and parallel cables are connected to pin 1 of the related connector Step 7...

Page 40: ...ess End to start the installation Step 4 The screen will show the dialog box to ask you to type the WIN31 s path The default is C WINDOWS Step 5 Follow the onscreen messages When the setup is completed the system will generate the message as follows Installation is done Change to your Windows directory and type SETUP to run the Windows Setup program Choose one of the new drivers marked with an Ple...

Page 41: ... ROM pattern files are named with the name assigned by the ROM_NAME in the PGF and the extension names are R01 R02 etc To generate ROM pattern files The ROM File Generator main menu will be displayed on the screen There are 7 options on the main menu They serve the following functions Quit to DOS Quits and exits to the DOS OS Shell Exits from the RFG temporarily to the DOS prompt Type EXIT to retu...

Page 42: ...going to be copied This file can have any DOS filename but the extension name must be PGF For example the followings are valid filenames RFGDEMO PGF MYRFG PGF MSDOS PGF An examples of the PGF file is as follows ROM_NAME TEST1 ROM pattern file name is TEST1 The output file names will be TEST1 R01 TEST1 R02 etc DOS_DRIVE C DOS system drive unit is drive C If user does not want to copy DOS system fil...

Page 43: ...u have to write or update data on your FLASH SRAM disk you can use the software write protect instead of hardware write protect The software write protect function is enabled or disabled by writing a data to an I O port 5 3 3 Enable the Software Write Protect Writes data 80h to the base port 0 address Example 1 in assembly language MOV DX 210H If the base I O address is 210H MOV AL 80H Enable byte...

Page 44: ...ry time before it times out If your program fails to trigger or disable this timer before it times out because of a system hang up it will generate a reset signal to reset the system The time out period can be programmed to be from 3 to 42 seconds Watchdog Register Time Base Counter and Compartor Enable D7 Time Factor D0 D2 Write and Trigger Watchdog LED RESET Figure 5 1 Watchdog Block Diagram 1 S...

Page 45: ...e watchdog times out the following table lists the relation of timer factors between time out periods And if you use the IRQ11 signal to warn your program when the watchdog times out please enter the BIOS Setup in the Peripheral Setup menu set the two items OnBoard PCI IDE and IDE Prefetch to Primary Time Factor Time Out Period Seconds 0E0H 3 0E1H 6 0E2H 12 0E3H 18 0E4H 24 0E5H 30 0E6H 36 0E7H 42 ...

Page 46: ... WD_REG TIMER_FACTOR etc 4 Disable Watchdog Timer To disable the watchdog timer simply write a 00H to the watchdog register 3000 REM Points to command register 3010 WD_REG BASE_PORT 3020 REM Timer factor 0 3030 TIMER_FACTOR 0 3040 REM Output factor to watchdog register 3050 OUT WD_REG TIMER_FACTOR etc 5 4 2 Built in Watchdog Timer Once you have enabled the watchdog timer your program must trigger ...

Page 47: ...out you should initialize the IRQ interrupt vector and enable the second interrupt controller 8259 PIC in order to enable the CPU to process this interrupt An interrupt service routine is required too 2 Before you initiate the interrupt vector of the IRQ and enable the PIC please enable the watchdog timer previously Otherwise the watchdog timer will generate an interrupt at the time the watchdog t...

Page 48: ...ter you need to unlock the register at first and lock it again after finishing the operation a Unlock Configuration Register Mov al 13h Out 22h al Nop Nop Mov al 0c5h Out 23h al Nop Nop b Lock Configuration Register Mov al 13h Out 22h al Nop Nop Mov al 00h Out 23h al Nop Nop c Read the Value in the Configuration Register Example 1 Read data from INDEX 3Ch Unlock_Cfg_Reg Unlock configuration regist...

Page 49: ...e Data to Configuration Register Example 1 Write data 68h to INDEX 3Bh Unlock_Cfg_Reg Unlock configuration register Mov al 3bh Points to index 3bh Out 22h al Nop Nop Mov al 68h Out 23h al Write data Nop Nop Lock_Cfg_Reg Lock configuration register ...

Page 50: ...your data on small page 5V FLASH or SRAM disk from accidental deletion or overwrite Data retention of SRAM is ensured by an on board Lithium battery or an external battery pack that could be connected to the AR B1380 AR B1380A Caution 1 DRAM U9 on board is a standard memory if you want to expand memory capacity you should follow the default order the priority is U4 and then SIMM1 2 When SIMM1 appl...

Page 51: ...293H 294 295H OFF ON 310 313H 314 315H ON ON 390 393H 394 395H X X 76H 77H Table 6 1 I O Port Address Select 6 2 3 SSD D O C Setup Before you are going to set up S S D or D O C you must adjust the settings of JP10 and SW2 3 SW2 4 JP10 is a 6 pin jumper located between M3 It is used to select the SSD or DOC memory that the system is being installed SW2 3 SW2 4 are used to select the memory base add...

Page 52: ...dition the SSD BIOS of AR B1380 AR B1380A will set the drive letter of the SSD to the desired drive letter automatically The SSD BIOS will simulate one disk drive when only FLASH EPROM or SRAM starting from MEM1 socket is installed The drive numbers with respect to the switch setting when the AR B1380 AR B1380A simulates single disk drives SW2 5 SW2 6 Occupies floppy disk number SSD OFF OFF 0 or 1...

Page 53: ...380 AR B1380A SSD BIOS the disk number will be 0 A under advanced cmos setup menu you can change the disk number from 0 A to 1 B of network at the first boot device by pressing the ESC during system bootup 2 Disk Drive Name Arrangement If any logical hard disk drives exist in your system there will also be a different disk number depending on which version DOS you are using The solid state disk dr...

Page 54: ...ips into all of the sockets The number of SRAM chips required depends on your RAM disk capacity The number of EPROM chips required depends on the total size of files that you plan to copy onto the ROM disk and whether or not it will be bootable Insert the first memory chip into MEM1 if you are going to configure it as a ROM or SRAM disk If you use a combination of ROM and RAM then insert the FLASH...

Page 55: ... careful with these two jumpers during installation 6 4 ROM DISK INSTALLATION This section describes the various types of SSDs installation steps as follows 6 4 1 UV EPROM 27Cxxx 1 Switch and Jumper Setting Step 1 Use jumper block to set the memory type as ROM FLASH Step 2 Select the proper I O base port firmware address disk drive number and EPROM type on SW2 Step 3 Insert programmed EPROM s or F...

Page 56: ...ttern files edited by the user Step 4 Under DOS prompt type the command as follows C RFG file name of PGF Step 5 In the RFG EXE main menu choose the Load PGF File item that is PGF file Step 6 Choose the Generate ROM File s the tools program will generate the ROM files for programming the EPROMs Step 7 Program the EPROMs Using the instruments of the EPROM writer to load and write the ROM pattern fi...

Page 57: ...ess disk drive number and large page 5V FLASH type on SW2 Step 3 Insert programmed EPROM s or FLASH s chips into sockets starting at MEM1 SW2 1 SW2 6 Š Off SW2 7Š On Figure 6 6 5V Large FLASH 29FXXX Switch Setting SW2 8 Š Off Function M1 M3 Setting JP6 Setting 5V 12V FLASH 64Kx8M 128Kx8 256Kx8 5V FLASH 512K 8 only Figure 6 7 Large Page 5V FLASH Jumper Setting 2 Software Programming Then you should...

Page 58: ... AR B1380 AR B1380A board into any free slot of your computer 6 4 3 Small Page 5V FLASH ROM Disk 1 Switch and Jumper Settings Step 1 Use jumper block to set the memory type as ROM FLASH Step 2 Select the proper I O base port firmware address disk drive number and EPROM type on SW2 Step 3 Insert programmed EPROM s or FLASH s chips into sockets starting at MEM1 SW2 1 SW2 7Š Off SW2 8 Š On Figure 6 8...

Page 59: ...during the system boot up this enables you to enter the FLASH setup program If the program does not show up check the switch setting of SW2 Step 2 Use Page Up Page Down Right and Left arrow keys to select the correct FLASH memory type and how many memory chips are going to be used Step 3 Press the F4 key to save the current settings Step 4 After the DOS is loaded use the DOS FORMAT command to form...

Page 60: ... disk Step 1 Use jumper block to select the memory type as SRAM refer Step 2 Select the proper I O base port firmware address and disk drive number on SW2 Step 3 Insert SRAM chips into sockets starting from MEM1 Step 4 Turn on power and boot DOS from hard disk drive or floppy disk drive Step 5 Use the DOS command FORMAT to format the RAM disk If you are installing SRAM for the first time To format...

Page 61: ...4 Select the proper I O base port firmware address and disk drive number on SW2 Step 5 Turn on power and boot DOS from hard disk drive or floppy disk drive Step 6 Use the DOS command FORMAT to format the RAM disk C FORMAT RAM disk letter U Step 7 If 5V FLASH small page is being used for the first time And then use the DOS command FORMAT to format the FLASH disk Step 8 If large page 5V FLASH is bei...

Page 62: ...l capability In the worst situation the user may have corrupted the original settings set by the manufacturer After the computer turned on the BIOS will perform a diagnostics of the system and display the size of the memory that is being tested Press the Del key to enter the BIOS Setup program and then the main menu will show on the screen The BIOS Setup main menu includes some options Use the Up ...

Page 63: ...S manual Floppy Setup The Standard CMOS Setup option records the types of floppy disk drives installed in the system To enter the configuration value for a particular drive highlight its corresponding field and then select the drive type using the left or right arrow key Hard Disk Setup The BIOS supports various types for user settings The BIOS supports Pri Master and Pri Slave so the user can ins...

Page 64: ... reboot and investigate your system The default setting is Disabled This setting is recommended because it conflicts with new operating systems Installation of new operating system requires that you disable this to prevent write errors 7 3 ADVANCED CMOS SETUP The Advanced CMOS SETUP option consists of configuration entries that allow you to improve your system performance or let you set up some sy...

Page 65: ...ions Disabled enabled Floppy Drive Swap The option reverses the drive letter assignments of your floppy disk drives in the Swap A B setting otherwise leave on the default setting of Disabled No Swap This works separately from the BIOS Features floppy disk swap feature It is functionally the same as physically interchanging the connectors of the floppy disk drives When the setting is Enabled the BI...

Page 66: ...e the BIOS Setup is executed If Always is chosen a user password prompt appears every time the computer is turned on If Setup is chosen the password prompt appears if the BIOS executed Available options Setup Always Wait for F1 If Error AMIBIOS POST error messages are followed by Press F1 to continue If this option is set to Disabled the AMIBIOS does not wait for you to press the F1 key after an e...

Page 67: ...emory address Available options Disabled C8000H D0000H D8000H E0000H E8000H 7 4 ADVANCED CHIPSET SETUP This option controls the configuration of the board s chipset Control keys for this screen are the same as for the previous screen Figure 7 4BIOS Advanced Chipset Setup AT Bus Clock This option sets the polling clock speed of ISA Bus PC 104 Available options 14 318 2 PLCK2 3 PLCK2 4 PLCK2 5 PLCK2...

Page 68: ...k 7 159 MHz 7 159MHz PCLK2 2 PCLK2 3 PCLK2 3 PCLK2 4 PCLK2 4 PCLK2 5 PCLK2 5 PCLK2 6 PCLK2 6 PCLK2 8 PCLK2 8 PCLK2 10 PCLK2 10 PCLK2 12 Available options Enabled Disabled ISA Memory High Speed This option allows the ISA card to operate at higher ATCLK during specific memory accessing cycles Same as ISA I O High Speed the above table describes the frequency that it can improve Available options Ena...

Page 69: ...hat IRQ every certain period of time Available options IRQ3 IRQ4 IRQ10 IRQ10 IRQ11 IRQ12 IRQ12 IRQ12 IRQ15 RESET 7 5 PERIPHERAL SETUP This section is used to configure the peripheral features Hard Disk Delay If this option is set to Disabled and the system BIOS executes too fast the result is that the BIOS can t find the hard disk drive Therefore it is recommended to select a hard disk delay perio...

Page 70: ...rmal ECP EPP EPP version This option specifies the EPP version Available options Normal 1 9 1 7 Parallel Port IRQ This option selects the IRQ for the parallel port IRQ Available options 5 7 Parallel Port DMA Channel This option is only available if the setting for the parallel Port Mode option is ECP Available options 0 1 3 7 6 PASSWORD SETTING This BIOS Setup has an optional password feature The ...

Page 71: ...e a better chance of working when the system is having configuration related problems 7 7 1 Auto Configuration with Optimal Setting User can load the optimal default settings for the BIOS The Optimal default settings are best case values that should optimize system performance If CMOS RAM is corrupted the optimal settings are loaded automatically Load high performance settings Y N 7 7 2 Auto Confi...

Page 72: ...Flash EPROM will be programmed Press ENTER after inserting the file name or press ESC to exit Step 5 And then please enter the file name to the box of Enter File Name And the box of Message will show the notice as follow In the bottom of this window always show the gray statement Flash EPROM Programming is going to start System will not be usable until Programming of Flash EPROM is successfully co...

Page 73: ...nd 6 pin 2 0 mm JST connector Real Time Clock BQ3287MT or compatible chips System BIOS AMI flash BIOS Including SSD BIOS VGA BIOS AR B1380A only Watchdog Programmable watchdog timer Acrosser s standard and M6117C build in Solid State Disks Supports 3 sockets for up to 3MB 1 5MB 1 5MB EPROM Flash SRAM Can be configured as three socket SSD sockets or two SSD sockets and one D O C socket Speaker Onbo...

Page 74: ...m27C010 128Kx8 1M bits ATMEL AT27C010 128Kx8 1M bits FUJITSHU MBM27C1001 128Kx8 1M bits HITACHI HN27C101 128Kx8 1M bits INTEL D27C010 128Kx8 1M bits MITSHUBISHI M5M27C101 128Kx8 1M bits NEC D27C1001 128Kx8 1M bits NS NM27C010 128Kx8 1M bits SGS THOMSON M27C1001 128Kx8 1M bits TI TMS27C010 128Kx8 1M bits TOSHIBA TCS711000 128Kx8 1M bits AMD Am27C020 256Kx8 2M bits ATMEL AT27C020 256Kx8 2M bits FUJI...

Page 75: ... selected by SW2 3 SW2 4 The I O port address of the bank select register is base port 0 and the I O port address of the chip select register is base port 2 The following is the format of the bank select register and bank enable register Register I O Port D7 D6 D5 D4 D3 D2 D1 D0 Bank Select Register Base 0 WPE A6 A5 A4 A3 A2 A1 A0 Chip Select Register Base 2 0 0 0 1 CS1 CS0 X X Where WPE Write pro...

Page 76: ... B1380A The AR B1380 AR B1380A is using 27C020 256K 8 and the base port is H210 100 base_port H210 110 OUT base_port 0 H59 Example 2 Select the 40th bank of MEM3 on the AR B1380 AR B1380A The AR B1380 AR B1380A is using 27C040 512K 8 and the base port is H390 200 base_port H290 210 OUT base_port 0 HD7 ...

Page 77: ...1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 2 2 M1 M2 M3 MEM1 MEM2 MEM3 1 2 3 2 1 1 2 3 1 2 3 A B C A B C C B A A B C 1 2 3 1 1 BUS1 BUS2 CN1 CN2 CN3 CN4 DB2 1 SIMM1 CN9 H1 H2 H3 U15 105 104 1 U17 105 104 1 U7 DB1 CN7 CN8 CN5 J7 J4 J6 JP7 JP4 JP1 JP9 JP2 JP6 JP8 P1 P2 P3 P4 J5 JP3 JP5 JP10 P5 P6 P7 JP11 J8 J1 J3 J9 J2 U10 U14 U20 U8 U5 LED1 SW2 U9 U4 CN6 JP12 ...

Page 78: ...ntrol RS 485 s TXC communication 2 Send out one character Transmit Step 1 Enable the TXC signal and the bit 0 of the address of offset 4 sets to 1 Step 2 Send out the data Write this character to the offset 0 of the current COM port address Step 3 Wait for the buffer s data empty Check the transmitter holding register THRE bit 5 of the address of offset 5 and transmitter shift register TSRE bit 6 ...

Page 79: ...able transmitter by setting DTR ON 20 OUT H3FC INP H3FC OR H01 30 REM Send out one character 40 PRINT 1 OUTCHR 50 REM Check transmitter holding register and shift register 60 IF INP H3FD AND H60 0 THEN 60 70 REM Disable transmitter by resetting DTR 80 OUT H3FC INP H3FC AND HEF 90 RETURN c Receive one character from COM1 10 REM Check COM1 receiver buffer 20 IF LOF 1 256 THEN 70 30 REM Receiver buff...

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