AR-B1380/AR-1380A User’ s Guide
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2.3 KEYBOARD CONTROLLER
The 8042 processor is programmed to support a keyboard serial interface. The keyboard controller
receives serial data from the keyboard, checks its parity, translates scan codes, and presents it to the
system as a byte data in its output buffer. The controller can interrupt the system when data is placed in its
output buffer, or wait for the system to poll its status register to determine when data is available.
Data can be written to the keyboard by writing data to the output buffer of the keyboard controller.
Each byte of data is sent to the keyboard controller in series with an odd parity bit automatically inserted.
The keyboard controller is required to acknowledge all data transmissions. Therefore, another byte of data
will not be sent to the keyboard controller until an acknowledgment is received for the previous byte. The
“output buffer full” interruption may be used for both send and receive routines.
2.4 INTERRUPT CONTROLLER
The equivalent of two 8259 Programmable Interrupt Controllers (PIC) are included on the AR-B1380/AR-
B1380A board. They accept requests from the peripherals, resolve priorities on pending interrupts in
service, issue interrupt requests to the CPU, and provide vectors which are used as acceptance indexed by
the CPU to determine which interrupt service routine should be executed.
The following is the system interrupt levels:
IRQ8 : Real time clock
IRQ9 : Rerouting to INT 0Ah from hardware IRQ2
IRQ10 : LAN
IRQ11 : Reserved for watchdog
IRQ12 : Spare
IRQ13 : Math. coprocessor
IRQ14 : Hard disk adapter
IRQ15 : Reserved for watchdog
In
Interrupt Level
NMI
CTRL1
IRQ 0
IRQ 1
IRQ 2
IRQ 3
IRQ 4
IRQ 5
IRQ 6
IRQ 7
CTRL2
Parity check
Description
Serial port 2
Serial port 1
Parallel port 2
Floppy disk adapter
Parallel port 1
System timer interrupt from timer 8254
Keyboard output buffer full
Figure 2-1 Interrupt Controller
Summary of Contents for AR-B1380
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