Acromag IP440 Series, User Manual

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SERIES IP440 INDUSTRIAL I/O PACK 32-CHANNEL ISOLATED DIGITAL INPUT MODULE
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Write Mask Register & Enhanced Mode Select Register
(Standard Mode, Port 7, Read/Write)
The ASIC used by the IP440 is capable of output. However,
the ports of this model are intended for input only and writes to
these ports should be avoided. This register is used to mask the
ability to write data to the four I/O ports of this model. Writing a
‘1’ to bits 0-3 of the Mask Register will mask ports 0-3
respectively, from inadvertent writes. A read of this register will
return the status of the mask in bits 0-3.
Standard Mode Write Mask Register (Port 7)
BIT WRITE TO REGISTER READ FROM REGISTER
0 Port 0 Write Mask Port 0 Write Mask
1 Port 1 Write Mask Port 1 Write Mask
2 Port 2 Write Mask Port 2 Write Mask
3 Port 3 Write Mask Port 3 Write Mask
4-7 NOT USED NOT USED
Bits 4-7 of this register are not used. On power-up reset, this
register defaults to the unmasked state, allowing writes to the
output ports.
This register is also used to select the Enhanced Mode of
operation. To switch to Enhanced Mode, four unique bytes must
be written to port 7, in consecutive order, without doing any reads
or writes to any other port and with interrupts disabled. The data
pattern to be written is 07H, 0DH, 06H, and 12H, in order, and
this must be written immediately after reset or power-up.
ENHANCED MODE
BANK 0 REGISTERS
Port Registers
(Enhanced Mode Bank 0, Ports 0-3, Read, Write Restricted)
Four input registers are provided to monitor 32 possible input
points. Data is read from one of four groups (Ports 0-3) of eight
input lines, as designated by the address. Each port assigns the
least significant data line (D0) to the least significant input line of
the port grouping (e.g. IN00 of port 0 to D0). A read of this
register returns the status (ON/OFF) of the input signal. Although
the ASIC used by this model is capable of output, the IP440 is
intended for input only and writes to these registers should be
blocked. Writing ‘1’ to this register will cause the input to always
read as 0, and changes in the input will be ignored (until a 0 is
written or a reset occurs). A Mask Register is used to disable
writes to ports intended for input only. That is, each port (group
of 8 input lines) should be masked from writes (see below).
Write Mask Register And Bank Select Register 0
(Enhanced Mode Bank 0, Port 7, Read/Write)
The ASIC used by the IP440 is capable of output. However,
the ports of this model are intended for input only and writes to
these ports should be avoided. This register is used to mask the
ability to write data to the four I/O ports of this model. Writing a
‘1’ to bits 0-3 of the Mask Register will mask ports 0-3
respectively, from inadvertent writes. A read of this register will
return the status of the mask in bits 0-3.
Enhanced Mode Write Mask Register (Port 7)
BIT WRITE TO REGISTER READ FROM REGISTER
0 Port 0 Write Mask Port 0 Write Mask
1 Port 1 Write Mask Port 1 Write Mask
2 Port 2 Write Mask Port 2 Write Mask
3 Port 3 Write Mask Port 3 Write Mask
4-5 NOT USED NOT USED
6 Bank Select Bit 0 Bank Status Bit 0
7 Bank Select Bit 1 Bank Status Bit 1
Bits 6 & 7 of this register are used to select/monitor the bank
of registers to be addressed. In Enhanced Mode, three banks
(banks 0-2) of eight registers may be addressed. Bank 0
registers are similar to the Standard Mode bank of registers.
Bank 1 allows the 32 event inputs to be monitored and controlled.
Bank 2 registers control the debounce circuitry of the event
inputs. Bits 7 and 6 select the bank as follows:
Enhanced Mode Bank Select
Bit 7 Bit 6 BANK OF REGISTERS
00 Bank 0 - Read Input Signals
01 Bank 1 - Event Status/Clear
10 Bank 2 - Event Debounce Control, Clock,
and Duration
11 INVALID - DO NOT WRITE
On power-up reset, this device is put into the Standard Mode
and this register defaults to the unmasked state (allowing writes
to the ports which should be avoided), and bank 0 (Default).
BANK 1 REGISTERS
Event Sense Status & Clear Registers For IN00-IN31
(Enhanced Mode Bank 1, Ports 0-3, Read/Write)
Each input line of each port includes an event sense input.
Reading each port will return the status of each input port’s sense
lines. Writing ‘0’ to a bit position of each port will clear the event
on the corresponding line. When writing ports 0-3 of Enhanced
Mode bank 1, each data bit written with a logic 0 clears the
corresponding event sense flip/flop. Further, each data bit of
ports 0-3 must be written with a 1 to re-enable the corresponding
event sense input after it is cleared. Reading ports 0-3 of the
Enhanced Mode bank 1 returns the current event sense flip/flop
status.
Port 0 Event Sense/Status Register (Ports 1-3 are Similar)
BIT READ PORT WRITE “0” WRITE “1”
0 Port 0 IN00
Event Status Clear IN00 Event
Sense Flip/Flop Re-enable IN00
Event Sense
1 Port 0 IN01
Event Status Clear IN01 Event
Sense Flip/Flop Re-enable IN01
Event Sense
2 Port 0 IN02
Event Status Clear IN02 Event
Sense Flip/Flop Re-enable IN02
Event Sense
3 Port 0 IN03
Event Status Clear IN03 Event
Sense Flip/Flop Re-enable IN03
Event Sense
4 Port 0 IN04
Event Status Clear IN04 Event
Sense Flip/Flop Re-enable IN04
Event Sense
5 Port 0 IN05
Event Status Clear IN05 Event
Sense Flip/Flop Re-enable IN05
Event Sense
6 Port 0 IN06
Event Status Clear IN06 Event
Sense Flip/Flop Re-enable IN06
Event Sense
7 Port 0 IN07
Event Status Clear IN07 Event
Sense Flip/Flop Re-enable IN07
Event Sense
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