Acromag IP440 Series, User Manual

Page: 12 / 22

SERIES IP440 INDUSTRIAL I/O PACK 32-CHANNEL ISOLATED DIGITAL INPUT MODULE
___________________________________________________________________________________________
- 11 -
Notes (Table 3.2):
1. The IP model number is represented by a two-digit code
within the ID PROM (P440 model is represented by 10 Hex).
2. Execution of an ID PROM read requires 0 wait states.
THE EFFECT OF RESET
A power-up or bus-initiated software reset will place the
module in the Standard Operating Mode (input only, no event
sensing, no interrupts, and no debounce). A reset will also clear
the mask register and enable writes to the input points of the
ASIC (input lines of this model should be masked from writes).
Further, all event inputs are reset, set to positive events, and
disabled following reset. A false input signal is ensured for inputs
left floating (i.e. reads as 0). The Interrupt Enable Register (IER)
and Interrupt Vector Register (IVR) are also cleared (except for
IER generated software resets).
Another form of software reset (IER register initiated) acts
similar to a carrier or power-up reset, except that it is not driven
by the carrier and only resets the digital ASIC chip installed on
the module. As such, the Interrupt Vector Register and Interrupt
Enable Register are not cleared for a software reset initiated in
this manner since they are implemented within the PLD (writing a
1 to the bit 1 position of the IER Register will cause this type of
software reset to occur). Reset in this manner has been provided
for use with some ISA carriers which do not implement the bus
reset control, or when the interrupt vector and interrupt enable
information must be preserved following reset.
IP440 PROGRAMMING
Acromag provides an Industrial I/O Pack Software Library
diskette (Model IPSW-LIB-M03, MSDOS format) to simplify
communication with the board. Example software functions are
provided for both ISAbus (PC/AT) and VMEbus applications. All
functions are written in the “C” programming language and can be
linked to your application. For more details, refer to the
“README.TXT” file in the root directory on the diskette and the
“INFO440.TXT” file in the appropriate “IP440” subdirectory off of
“\VMEIP” or “\PCIP”, according to your carrier.
Basic Input Operation
Note that the input lines of this module are assembled in
groups of eight. Each group of eight lines is referred to as a port.
Ports 0-3 control and monitor input lines 0-31. Additionally, ports
are grouped eight to a bank. There are four banks of ports used
for controlling this module (Standard Mode, plus Enhanced Mode
Banks 0, 1, and 2), plus 2 additional registers for enabling the
interrupt request line, generating a software reset, and storing the
interrupt vector.
Each port input line is bipolar and accepts both positive and
negative input voltages in two ranges according to the model
number. Individual input lines of a port share a common signal
connection with each other. Separate commons are provided for
each port to facilitate port-to-port isolation. A high signal is
derived from the absolute value of the input voltage measured
between the input line and the port common for the input ranges
of 4-18V (IP440-1 models), 16-40V (IP440-2 models), and 38-
60V (IP440-3 models). Inputs are non-inverting and inputs left
floating (not recommended) will register a low (false=0) input
indication.
In both the Standard and Enhanced operating modes, each
group of eight parallel input lines (a port) are isolated and gated
to the data bus D0..D7 lines. A high input will read as “1” and all
inputs include hysteresis and programmable debounce. Because
the ASIC used by this model is capable of output, individual ports
should be masked from writes to the port since they are intended
for input only.
Enhanced Operating Mode
In the Enhanced Mode of operation, each port input may act
as an event sensor and generate interrupts. Likewise,
programmable debounce logic is also available. Event sensing is
used to selectively sense high-to-low level, or low-to-high level
transitions on the input lines at the range thresholds of 4V (“-1”
units), 16V (“-2” units), and 38V (“-3” units). Event polarities may
be defined as positive or negative for individual nibbles (groups of
4 input lines, or half ports). Interrupts may also be triggered by
events. The optional debounce logic can act as a filter to
“glitches” or transients present on received signals.
Because the ASIC used by this model is capable of I/O, while
the module is intended for input only, individual input ports should
be masked from writes to the port. Otherwise, writing a “1” to an
input line will cause the input to always read 0 (until a “0” is
written or a reset occurs).
The Enhanced Mode is entered by writing four unique bytes
to the Standard Mode Port 7 register, in consecutive order,
without doing any reads or writes to any other port and with
interrupts disabled. The data pattern to be written is 07H, 0DH,
06H, and 12H, and this must be written immediately after reset or
power-up.
In Enhanced Mode, there are three groups (or banks) of eight
registers or ports. The first group, bank 0, provides register
functionality similar to Standard Mode (input level monitoring).
The second group, bank 1, provides monitor and control of the
event sense inputs. The third group, bank 2, is used to configure
the debounce circuitry for each input while in the Enhanced
Mode.
Event Sensing
The IP440 has edge-programmable event sense logic built-in
for all 32 input lines, IN00 through IN31. Event sensing may be
configured to generate an interrupt to the carrier, or to merely
reflect the interrupt internally. Event sensing is enabled in
Enhanced Mode only and inputs can be set to detect positive or
negative events, on a nibble-by-nibble (group of 4 input lines)
basis. The event sensing is enabled on an individual channel
basis. You can combine event sensing with the built-in debounce
control circuitry to obtain “glitch-free” edge detection of incoming
signals.
To program events, determine which input lines are to have
events enabled and which polarity is to be detected, high-to-low
level transitions (negative) or low-to-high level transitions
(positive). Set each half-port (nibble) to the desired polarity, then
enable each of the event inputs to be detected. Optionally, if
interrupt requests are desired, load the interrupt vector register
and enable the interrupt request line. Note that all event inputs
are reset, set to positive events, and disabled after a power-up or
software reset has occured.
Artisan Scientific - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisan-scientific.com