Acromag IP440 Series, User Manual

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SERIES IP440 INDUSTRIAL I/O PACK 32-CHANNEL ISOLATED DIGITAL INPUT MODULE
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Change-Of-State Detection
Change-of-State signal detection requires that both a high-to-
low and low-to-high signal transition be detected. On the IP440,
if change-of-state detection for an input signal is desired, two
channels connected to the same input signal would be required--
one sensing positive transitions, one sensing negative transitions.
Since channel polarity is programmable on a nibble basis (group
of four), the first nibble of a port could be configured for low-to-
high transitions, the second nibble for high-to-low transitions. As
such, up to 16 change-of-state detectors may be configured.
Debounce Control
Debounce control is built into the on-board digital ASIC
employed by the IP440 and is enabled in the Enhanced Mode
only. With debounce, an incoming signal must be stable for the
entire debounce time before it is recognized as a valid input or
event at the ASIC input. Note that the debounce time applies at
the ASIC input and does not include the optocoupler delay. You
can combine debounce with event sensing to obtain “glitch-free”
edge detection of incoming signals for all 32 channels. That is,
the debounce circutry will help filter out “glitches” or transients
that can occur on received signals, for error-free edge detection
and increased noise immunity.
The debounce circuitry uses the 8MHz carrier clock to derive
the debounce times (see the Debounce Clock Select register to
enable the 8MHz clock to be used). With the 8MHz carrier clock,
a debounce value of 3-4us, 48-64us, 0.75-1ms, or 6-8ms may be
selected (see the Debounce Duration Register). As such, an
incoming ASIC signal must be stable for the debounce time
before it is recognized as a valid input or event.
Upon initialization of the debounce circuitry, be sure to delay
at least the programmed debounce time before reading any of the
input ports or event signals to ensure that the input data is valid
prior to being used by the software.
Interrupt Generation
This model provides control for generation of interrupts on
positive or negative events, for all 32 channels. Interrupts are
only generated in the Enhanced Mode for event channels when
enabled via the Event Sense/Status Register. Writing 0 to the
corresponding event sense bit in the Event Sense/Status
Register will clear the event sense flip/flop. Successive interrupts
will only occur if the event channel has been reset by writing a 1
to the corresponding event sense bit in the Event Sense/Status
Register (after writing 0 to clear the event sense flip/flop).
Interrupts may be reflected internally and reported by polling the
module, or optionally reported to the carrier by enabling control of
the Interrupt Request line (Intreq0). Control of this line is initiated
via Bit 0 of the Interrupt Enable Register (IER).
After pulling the IntReq0 line low and in response to an
Interrupt Select cycle, the module will read (serve) the 8-bit
interrupt vector stored in the Interrupt Vector Register. The
IntReq0 line will be released as soon as the conditions generating
the interrupt have been cleared or return to normal, and the event
sense flip/flop has been cleared by writing 0 to the corresponding
bit position of the Event Sense Status Register, or until the
Interrupt Enable Register bit is cleared. Zero wait states are
required to complete an interrupt select cycle.
Note that the state of the inputs (on/off) is determined by
reading the corresponding port address while in bank 0 of the
Enhanced Mode. However, the event sense status can only be
read by reading the corresponding port address while in bank 1 of
the Enhanced Mode. Remember, the event sense status is a flag
that is raised when a specific positive or negative transition has
occurred for a given input point, while the state refers to its
current level.
Note that the Interrupt Enable Register and Interrupt Vector
Register are cleared following a power-up or bus initiated
software reset, but not a software reset initiated via writing a one
to bit 1 of the Interrupt Enable Register. Keep this in mind when
you wish to preserve the information in these two registers
following a reset.
Programming Example
The following example outlines the steps necessary to
configure the IP440 for Enhanced Mode operation, to setup
event-generated interrupts, configure debounce, and read and
write inputs. It is assumed that the module has been reset and
no prior (non-default) configuration exists.
For this example, we will configure port 0 input points as a
four-channel change-of-state detector. For change-of-state
detection, both positive and negative polarities must be sensed
and thus, two channels are required to detect a change-of-state
on a single input signal. IN00-IN03 will be used to detect positive
events (low-to-high transitions), IN04-IN07 will be used to detect
negative events (high-to-low transitions). IN00 and IN04 will be
tied to the first input signal, IN01 & IN05 to the second, IN02 &
IN06 to the third, and IN03 & IN07 to the fourth. Any change-of-
state detected on these input signal lines will cause an interrupt
to be generated.
1. After power-up or reset, the module is always placed in the
Standard Operating Mode. To switch to the Enhanced Mode,
execute four consecutive write cycles to port 7 with the
following data: 07H first, followed by 0DH, followed by 06H,
then 12H.
At this point, you are in Enhanced Mode bank 0. Port 7
would now be used to access register banks 1 & 2.
2. Write 80H to the port 7 address to select register bank 2
where debounce will be configured for our port 0 input
channels.
At this point, you are in Enhanced Mode Bank 2 where
access to the debounce configuration registers is obtained.
3. We need to enable the 8MHz system clock to generate our
debounce time. By default, the debounce clock is not
enabled. Select the 8MHz system clock as the debounce
clock by writing 01H to the port 3 address of this bank
(Debounce Clock Select Register).
4. The default debounce duration is 3-4us with the 8MHz clock
enabled in step 3. This time applies to the ASIC input signal
and does not include optocoupler delay. Write 01H to the
port 1 address of this bank to select a 48-64us debounce
time (Debounce Duration Register 0). An incoming signal
must be stable for the entire debounce time before it will be
recognized as a valid input transition by the ASIC.
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