SERIES IP440 INDUSTRIAL I/O PACK 32-CHANNEL ISOLATED DIGITAL INPUT MODULE
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Table 3.1B: IP440 R/W Space Address (Hex) Memory Map
EVEN
Base
Addr+
MSB
D15 D08
LSB
D07 D00
ODD
Base
Addr+
ENHANCED MODE, REGISTER BANK [1] DEFINITIONS:
00
Not Driven
1
READ - Port 0
Event Sense Status Reg.
(Port 0 Input points 0-7)
01
00
Not Driven
1
WRITE - Port 0
Event Sense Clear Reg
(Port 0 Input points 0-7)
01
02
Not Driven
1
READ - Port 1
Event Sense Status Reg.
(Port 1 Input points 8-15)
03
02
Not Driven
1
WRITE - Port 1
Event Sense Clear Reg
(Port 1 Input points 8-15)
03
04
Not Driven
1
READ - Port 2
Event Sense Status Reg.
(Port 2 Input points 16-23)
05
04
Not Driven
1
WRITE - Port 2
Event Sense Clear Reg
(Port 2 Input points 16-23)
05
06
Not Driven
1
READ - Port 3
Event Sense Status Reg.
(Port 3 Input points 24-31)
07
06
Not Driven
1
WRITE - Port 3
Event Sense Clear Reg
(Port 3 Input points 24-31)
07
08
Not Driven
1
READ - Port 4
NOT USED
09
08
Not Driven
1
WRITE - Port 4
NOT USED
09
0A
Not Driven
1
READ - Port 5
NOT USED
0B
0A
Not Driven
1
WRITE - Port 5
NOT USED
0B
0C
Not Driven
1
READ - Port 6
Event Status for Ports 0-3
and Interrupt Status Reg.
0D
0C
Not Driven
1
WRITE - Port 6
Event Polarity Control
Register for Port 0-3
0D
0E
Not Driven
1
READ - Port 7
Current Bank Status Reg.
0F
0E
Not Driven
1
WRITE - Port 7
Bank Select Register
0F
ENHANCED MODE, REGISTER BANK [2] DEFINITIONS:
00
Not Driven
1
READ/WRITE - Port 0
Debounce Control Register
(for Ports 0-3)
01
02
Not Driven
1
READ/WRITE - Port 1
Debounce Duration Reg. 0
(for Ports 0-3)
03
04
Not Driven
1
NOT USED
05
06
Not Driven
1
WRITE ONLY - Port 3
Debounce Clock Select
07
08
↓
0C
Not Driven
1
Port 4,5,6
NOT USED
2
09
↓
0D
0E
Not Driven
1
READ/WRITE - Port 7
Bank Status/Select
Register
0F
Table 3.1B: IP440 R/W Space Address (Hex) Memory Map
EVEN
Base
Addr+
MSB
D15 D08
LSB
D07 D00
ODD
Base
Addr+
INDEPENDENT FIXED FUNCTION REGISTERS:
10
↓
1C
NOT USED
2
11
↓
1D
1E
Not Driven
1
READ/WRITE
Interrupt Enable Register
(Bit 0=1 enables
INTREQ0)
& Software Reset
Generator (Bit 1=1
Generates Reset)
1F
20
↓
2C
NOT USED
2
21
↓
2D
2E
Not Driven
1
READ/WRITE
Interrupt Vector Register
2F
30
↓
7E
NOT USED
2
31
↓
7F
Notes (Table 3.1B):
1. The upper 8 bits of these registers are not driven and pullups
on the carrier data bus will cause these bits to read high (1’s).
2. The IP will not respond to addresses that are "Not Used".
3. All Reads and Writes are 0 wait state.
4. Writes to these registers are possible, but this model is
intended for input only and writes should not be done. Writes
to these registers may be blocked via the Write Mask
Register of Port 7.
5. The ASIC of this model is capable of a greater channel count,
but only 32 channels are used by this model, and as a result,
ports 4, 5, & 6 are not used.
REGISTER DEFINITIONS
STANDARD MODE REGISTERS
Port Registers
(Standard Mode, Ports 0-3, Read, Write Restricted)
Four registers are provided to monitor 32 possible input
points. Data is read from one of four groups of eight input lines
(Ports 0-3), as designated by the address and read and write
signals. Each port assigns the least significant data line (D0) to
the least significant input line of the port grouping (e.g. IN00 for
port 0 to D0). A read of this register returns the status (ON/OFF)
of the input point. Although the ASIC used by this model is
capable of output, the IP440 is intended for input only and writes
to these registers should be blocked. Writing ‘1’ to this register
will cause the input to always read as 0, and changes in the input
will be ignored (until a 0 is written or a reset occurs). A Mask
Register is used to disable writes to ports intended for input only.
That is, each port (group of 8 input lines) should be masked from
writes.
On power-up or reset, the ports are reset to 0, forcing the
outputs to be set high/OFF (outputs are not used by this model).
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Summary of Contents for IP440 Series
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