Acromag IP440 Series, User Manual

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SERIES IP440 INDUSTRIAL I/O PACK 32-CHANNEL ISOLATED DIGITAL INPUT MODULE
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This manual is presented using the “Big Endian” byte
ordering format. Big Endian is the convention used in the
Motorola 68000 microprocessor family and is the VMEbus
convention. In Big Endian, the lower-order byte is stored at odd-
byte addresses. Thus, byte accesses are done on odd address
locations. The Intel x86 family of microprocessors use the
opposite convention, or “Little Endian” byte ordering. Little
Endian uses even-byte addresses to store the low-order byte. As
such, use of this module on an ISAbus (PC/AT) carrier board will
require the use of the even address locations to access the 8-bit
data, while a VMEbus carrier will require the use of odd address
locations.
Note that some functions share the same register address.
For these items, the address lines are used along with the read
and write signals to determine the function required.
Standard (Default) Mode Memory Map
The following table shows the memory map for the Standard
Mode of operation. This is the Default mode reached after
power-up or system reset. Standard Mode provides simple
monitoring of 32 digital input lines without interrupts. Data is read
from or written to one of eight groups (ports) as designated by the
address and read and write signals. A Mask Register is used to
disable writes to input ports, since this model is intended for input
only. That is, the ASIC used by this model is capable of output,
and since this model is intended for input only, then each port
(group of 8 input lines) must be blocked (masked) from writes.
To switch to Enhanced Mode, four unique bytes must be
written to port 7, in consecutive order, without doing any reads or
writes to any other port and with interrupts disabled. The data
pattern to be written is 07H, 0DH, 06H, and 12H, and this must
be written after reset or power-up.
Table 3.1A: IP440 R/W Space Address (Hex) Memory Map
EVEN
Base
Addr+
MSB
D15 D08
LSB
D07 D00
ODD
Base
Addr+
STANDARD MODE (DEFAULT) REGISTER DEFINITIONS:
00
Not Driven
4
READ
1
- Port 0
Register IN00-IN07 01
02
Not Driven
4
READ
1
- Port 1
Register IN08-IN/15 03
04
Not Driven
4
READ
1
- Port 2
Register IN16-IN23 05
06
Not Driven
4
READ
1
- Port 3
Register IN24-IN31 07
08
Not Driven
4
READ/WRITE
2
- Port 4
NOT USED 09
0A
Not Driven
4
READ/WRITE
2
- Port 5
NOT USED 0B
0C
Not Driven
4
READ/WRITE
2
- Port 6
NOT USED 0D
0E
Not Driven
4
READ/WRITE - Port 7
WRITE MASK REGISTER
AND
ENHANCED MODE
SELECT REGISTER
3
0F
10
↓
7E
NOT USED
5
11
↓
7F
Notes (Table 3.1A):
1. Writes to these registers are possible, but this model is
intended for input only and writes should not be done. Writes
to these registers may be blocked via the Write Mask
Register of Port 7.
2. The ASIC of this model is capable of a greater channel count,
but only 32 channels are used by this model, and as a result,
ports 4, 5, & 6 are not used.
3. Writing four unique bytes (07H, 0DH, 06H, and 12H) to port 7,
in consecutive order, will switch to Enhanced Mode. Do this
without doing any reads or writes to any other port, with
interrupts disabled, and after reset or power-up.
4. The upper 8 bits of these registers are not driven and pullups
on the carrier data bus will cause these bits to read high (1’s).
5. The IP will not respond to addresses that are "Not Used".
Enhanced Mode Memory Maps
The following table shows the memory maps used for the
Enhanced Mode of operation. Enhanced Mode includes the
same functionality of Standard Mode, but allows each input port’s
event sense input and debounce logic to be enabled.
In Enhanced Mode, a memory map is given for each of 3
memory banks. The first memory bank (bank 0) has the same
functionality as the Standard Mode. Additionally, its port 7
register is used to select which bank to access (similar to
Standard Mode where port 7 was used to select the Enhanced
Mode). Bank 1 provides read/write access to the 32 event sense
inputs. Bank 2 provides access to the registers used to control
the debounce circuitry of these event sense inputs.
Table 3.1B: IP440 R/W Space Address (Hex) Memory Map
EVEN
Base
Addr+
MSB
D15 D08
LSB
D07 D00
ODD
Base
Addr+
ENHANCED MODE, REGISTER BANK [0] DEFINITIONS:
00
Not Driven
1
READ
4
- Port 0
Register IN00-IN07 01
02
Not Driven
1
READ
4
-Port 1
Register IN08-IN15 03
04
Not Driven
1
READ
4
- Port 2
Register IN16-IN23 05
06
Not Driven
1
READ
4
- Port 3
Register IN24-IN31 07
08
Not Driven
1
READ/WRITE
5
- Port 4
NOT USED 09
0A
Not Driven
1
READ/WRITE
5
- Port 5
NOT USED 0B
0C
Not Driven
1
READ/WRITE
5
- Port 6
NOT USED 0D
0E
Not Driven
1
READ - Port 7
READ MASK REGISTER
(Also Current Bank Status) 0F
0E
Not Driven
1
WRITE - Port 7
WRITE MASK REGISTER
(Also Bank Select
Register)
0F
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