IOS-EP2 I/O SERVER MODULE Cyclone II Based FPGA Module
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Acromag, Inc. Tel:248-295-0310 Fax:248-624-9234 Email:[email protected] http://www.acromag.com
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An example program written in C and available from Acromag,
implements configuration of the IOS-EP2 Series module over the IOS bus.
The program requires the configuration file to be in the Intel Hex format. For
information on generating hex files refer to the documentation supplied with
the EDK.
1. Prior to power-
up set the Configuration Jumper to “IOS BUS” as shown
in the JTAG Interface/Jumper Location drawing at the end of this
manual.
2. Start in the configuration mode. Upon system power-up, the IOS-EP2
module is in configuration mode. If the Altera FPGA is currently
configured and operational, configuration mode can be entered by
driving pin F3 of the Altera FPGA to a logic high via the control register
bit-0. Pin F3 is the Config_Enable signal which upon system power-up
is held high by a pull-up resistor.
3. You can verify that you are in configuration mode by reading ID space at
base a 0AH. The byte read will be 48H when in configuration
mode and 49H when in user mode.
4. Configuration is started by setting bit-0 of the control register, at base
a 00H, to a logic high.
5. This same register bit-0 must be read next. When read as a logic high
software can proceed to the data transfer phase. A polling method
should be used since this bit may not be read high for up to 160
seconds after the control bit is set high.
6. The status of the Altera FPGA during configuration can be monitored via
the Status register at base a 00H. Bit-1 monitors the Altera
nStatus signal which must remain high during configuration. Bit-2 of the
Status register reflects the Altera FPGA CONF_DONE signal. The
CONF_DONE signal must remain at a logic low until configuration has
completed.
7. Write program data, one byte at a time, to the Configuration Data
register at base a 02H.
8. Upon successful configuration, control of the IOS bus will automatically
be switched to user mode and the Altera FPGA will have control of the
IOS bus interface. It is good practice to issue a software reset prior to
operating the board.
Refer to the documentation provided with the IOS-EP2 EDK for further
information on programming methodologies.
The IOS-EP2 module can also implement configuration using a standard
JTAG interface. The JTAG interface can either program the FPGA directly
or program the FLASH configuration memory. When programming the
FPGA directly, the programming jumper may be in either position. Note that
the FPGA will require reprogramming after power down.
The following is the general procedure for direct programming of the
Altera FPGA using the JTAG interface.
1. Connect the 10-pin Altera JTAG cable (not included) to the board.
2. Power-up the carrier board.
3. Download the Configuration .sof file to the FPGA via JTAG using
Altera Quartus II software.
4. Upon successful configuration the board will be in User mode with
the Altera FPGA in control of the IOS bus interface. It is good
practice to issue a software reset prior to operating the board.
IOS-EP2 IOS Direct
Configuration Procedure
IOS-EP2 Direct JTAG
Configuration Procedure