IOS-EP2 I/O SERVER MODULE Cyclone II Based FPGA Module
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Acromag, Inc. Tel:248-295-0310 Fax:248-624-9234 Email:[email protected] http://www.acromag.com
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Interrupt Programming Example
1. Clear the Interrupt Enable Bits in the Carrier Board Status Register by
writing a "0" to bit 2 and bit 3.
2. Perform Specific IOS-EP20X Module Programming - see the Change-of-
State or Level (Polarity) Match programming examples that follow, as
required for your application.
3. Write a “1” to bit 2 of the Carrier Status/Control Register Module Interrupt
Enable bit to enable IOS module interrupts to the PCI bus.
Programming Example for Change-of-State Interrupts:
1. Select channel Change-of-
State interrupts by writing a “1” to each
channel‟s respective bit in the Interrupt Type Register.
Note that Change-Of-
State interrupts (specified with “1”) may be mixed with
polarity ma
tch interrupts (specified with “0”).
3. Enable individual input channel interrupts by writing a “1” to each
channel‟s respective bit in the Interrupt Enable Register.
4. Clear pending interrupts by writing a “1” to each channel‟s respective bit
in the Interrupt Status Register.
Change-of-State Interrupts may now be generated by the input channels
programmed above for any Change-Of-State transition.
Processing Change-of-State Interrupts:
1. Clear the interrupting channel(s) by writing a “1” to the appropriate bits in
the IOS-EP20X Interrupt Status Register.
Programming Example for Level (Polarity) Match Interrupts:
1. Select channel Polarity Match Interrupts by writing a “0” to each channel‟s
respective bit in the Interrupt Type Register. Note that Change-Of-State
interrupts (specified with “1”) may be mixed with Polarity Match Interrupts
(specified with “0”).
3. Select the desired polarity (High/Low) level for interrupts by writing a “0”
(Low), or “1” (High) level to each channel‟s respective bit in the Interrupt
Polarity Register.
4. Enable individual input channel interrupts by writing a “1” to each
channel‟s respective bit in the Interrupt Enable Register.
5. Clear pending interrupts by writing a “1” to each channel‟s respective bit
in the Interrupt Status Register.
Interrupts can now be generated by matching the input level with the
selected polarity for programmed interrupt channels.
Processing Level (Polarity) Match Interrupts:
1. Disable the interrupting channel(s) by writing a “0” to the appropriate bits
in the IOS-EP20X Interrupt Enable Register.
2. After the interrupt stimulus has been removed, clear the interrupting
channel(s) by writing a “1” to the appropriate bits in the IOS-EP20X Interrupt
Status Register.
If the input stimulus is still applied, this will not clear the Interrupt Status
Register bit and the interrupting channel(s) must remain disabled until the
interrupt stimulus has been removed. After removal of the input stimulus the
channel(s) may be cleared and re-enabled.
