IOS-EP2 I/O SERVER MODULE Cyclone II Based FPGA Module
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Acromag, Inc. Tel:248-295-0310 Fax:248-624-9234 Email:[email protected] http://www.acromag.com
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This section contains information regarding the design of the board. A
description of the basic functionality of the circuitry used on the board is also
provided. Refer to the IOS-EP2 Series Block Diagram drawing at the end of
this manual as you review this material.
The IOS Specification defines all IOS control signals with 5V signaling
levels. Since the Altera Cyclone II Field Programmable Gate Array (FPGA)
is not 5V tolerant, all signals are buffered using a Complex Programmable
Logic Device (CPLD). The worst case buffer propagation delay is 10nS.
This delay is significant if running the IOS-EP2 Series module at 32MHz.
Therefore it is recommended that 1 wait state be implemented for all IOS
read/write cycles. Furthermore, the direction control signals are required to
control the IOS Data bus. These signals are controlled from the FPGA. For
more information on implementation of this requirement, refer to the
documentation provided in the EDK. The Altera FPGA installed on the IOS
Module controls the interface to the carrier board per IOS Module
specification ANSI/VITA 4 1995. The supplied FPGA logic example
includes: address decoding, I/O and ID read/write control circuitry, interrupt
handling, and ID storage implementation.
The carrier to IOS module interface allows access to both ID and I/O
space via 16 or 8-bit data transfers. Read only access to ID space provides
the identification for the individual module (as given in Table 3.2) per the
IOS specification. Read and write accesses to the I/O space provide a
means to control the IOS-EP2.
The IOS-EP2 has 64K words of SRAM available. Read and write
accesses to the SRAM are implemented through the IOS module I/O space.
A start address is specified in the Memory Address register. This start
address will automatically be incremented by hardware for each access to
the Memory Data register.
The IOS-EP2 also has a Clock Generator chip. A clock frequency from
250KHz to 100MHz is programmable via the IOS module I/O space. The
generated clock frequency is input to the FPGA on pin 183. This clock can
be used to synchronize I/O operations with other IOS modules.
For the supplied FPGA configuration, digital input channels of this model
can be configured to generate interrupts for Change-Of-State (COS) and
input level (polarity) match conditions at enabled inputs. An 8-bit interrupt
service routine vector is provided during interrupt acknowledge cycles on
data lines D0...D7. The interrupt release mechanism employed is RORA
(Release On Register Access).
The field I/O interface to the carrier board is provided through connector
P2 (refer to Table 2.1).
Field I/O points are NON-ISOLATED
. This means
that the field return and logic common have a direct electrical connection to
each other. As such, care must be taken to avoid ground loops. Ignoring
this effect may cause operational errors, and with extreme abuse, possible
circuit damage.
4.0 THEORY OF
OPERATION
IOS BUS INTERFACE LOGIC
Interrupt Operation
FIELD INPUT/OUTPUT
