IOS-EP2 I/O SERVER MODULE Cyclone II Based FPGA Module
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Acromag, Inc. Tel:248-295-0310 Fax:248-624-9234 Email:[email protected] http://www.acromag.com
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All IOS-EP2 models have a standard Altera JTAG header. It readily
connects to any compatible Altera programming cable such as the
ByteBlaster 2 ® or MasterBlaster®. The JTAG interface pins connect only
to the Altera FPGA. This connection can be used to program the FPGA or
use the Altera debugging tool SignalTap 2®. The JTAG interface is
powered by 3.3V. Refer to the EDK documentation for further information of
the JTAG interface and programming procedures.
The IOS-EP2 Series interfaces to a 64K word SRAM device. This
memory interface utilizes the address signals RAMa1 to RAMa16, data
signals RAMd0 to RAMd15, and the read/write control signals nWE_RAM,
nBLE_RAM, nBHE_RAM, and nOE_RAM. The RAM device is the
Integrated Device Technology IDT71V016SA, GSI Technology part
GS71116A, or equivalent. A complete listing of the SRAM interface pin and
their assignments on the Cyclone II FPGA is available in the IOS-EP2-EDK.
The IOS-EP2 Series interfaces to the carrier board per IOS Module
specification ANSI/VITA 4 1995. The FPGA signals utilized are: 16 data
lines (DATA0 to DATA15), and six address lines A(1 to 6). The many
control lines that comprise the IOS bus include: IOS Reset, nIOsel, nIDsel,
nMEMsel, nINTsel, R_nW, nAck, nIntReq0, nIntReq1, nDMAReq0,
nDMAReq1, nDMAAck, nDMAend, nStrobe, nBS0, and nBS1. A complete
listing of the IOS interface pins and their assignment on the Cyclone II
FPGA is available in the IOS-EP2 EDK. The IOS bus 8MHz or 32MHz
clock signal is present on pin CLK8MZ. The function and timing
requirements of all IOS bus signals are specified in the ANSI/VITA 4 1995
specification. Copies of the ANSI/VITA 4 1995 specification are available
from VITA (www.vita.com).
A clock generator chip (Cypress CY22150) is available to provide a user
programmable clock frequency between 250KHz and 100MHz. A total of
four signals are utilized: Ref Clock, SCLK, SDATA, and Gen Clock as seen
in the tale below.
Signal
Description
Ref Clock
The Ref Clock or reference clock is
a 8MHz clock generated by the
FPGA from the IOS carrier clock
signal.
SCLK
This is the serial clock to the
CY22150. It is used for clock
frequency programming.
SDATA
The serial data is sent from the
FPGA to the CY22150 on this pin
for clock frequency programming.
Gen Clock
The clock frequency generated by
the CY22150 is input to the FPGA
on this pin.
The FPGA pin definitions are in the FPGA Programming Guide provided
in the IOS-EP2 Series Engineering Design Kit.
JTAG INTERFACE
EXAMPLE DESIGN
Memory Interface
IOS Bus Interface
Clock Generator Interface
FPGA Pin Definitions