IOS-EP2 I/O SERVER MODULE Cyclone II Based FPGA Module
__________________________________________________________________
__________________________________________________________________________
Acromag, Inc. Tel:248-295-0310 Fax:248-624-9234 Email:[email protected] http://www.acromag.com
10
Configuration Control/Status Register (Read/Write) Base Addr + 0H
This read/write register is used to initiate the reprogramming of the
Cyclone II FPGA and to monitor the status of the FPGA during
configuration. Bit 0 of this register is used to trigger FPGA programming.
Writing a logic “1” to bit 0 will enable a pulse on the FPGA nConfig signal. If
the IOS carrier is providing a 32MHz clock, the pulse length will be 40uS. If
the carrier provides a 8MHz clock, the pulse length will be 160uS. Bit-1
monitors the Altera nSTATUS signal which must remain high during
configuration. Bit-2 of the Status register reflects the status of the Altera
FPGA CONF_DONE signal. The CONF_DONE signal must remain at a
logic low until configuration has completed
.
Writing to either bits 1 or 2 will
have no effect. Bits 4 is the CRC_ERROR signal from the FPGA. This
function is disabled in the example program must be enabled within the
Quartus II software. Refer to the Cyclone II Manual for information on this
signal. Bit 5 is the value of MSEL0 as determined by the configuration
jumper. A logic high on this bit indicates that configuration will occur over
the IOS bus. A logic low indicates that the configuration data is loaded from
Flash. Bits 3, and 6 to 7 are not used and will return logic “0” when read.
Configuration Data Register (Write Only) Base Addr + 2H
This write only register is a conduit for the programming data file, when
configuring the IOS-EP2 module over the IOS bus. Prior to configuration
the user must write a logic “1” to bit zero of the Configuration Control/Status
Register. Then after bit 0 of the Configuration Control/Status register reads
logic low again (up to 160mS), the programming file is written to this register
one byte at a time. The data is transferred serially to the FPGA, therefore a
write to this register requires 8 wait states.
The IOS-EP2 module has three methods of configuration. The first is
configuring the Altera FPGA directly over the IOS Bus. This method uses
the passive serial scheme to directly program the FPGA. Note that this
scheme requires the FPGA to be reprogrammed after every power-up. The
second method is to configure the part directly using a JTAG interface. The
JTAG interface will automatically over-write any existing configuration and
can be completed at any time using a standard Altera JTAG download cable
such as the ByteBlaster 2 . This cable is NOT provided by Acromag.
Once again all programming is lost at power-down using the direct JTAG
configuration approach. Finally the IOS-EP2 Series module contains a
Flash Configuration Device (Altera EPCS4 or equivalent) that can be
programmed indirectly through the JTAG interface using the Altera Serial
Flash Loader. The Serial Flash Loader creates a logic bridge between the
Cyclone II JTAG interface and the controls of the FLASH device. This
bridge allows the user to program the Flash via the JTAG interface. The
FLASH device cannot be programmed through the IOS interface. This
method is recommended for debugged designs since the Flash device
programs the Altera FPGA at power-up. The programming procedures for
each of the three methods are below.
The IOS-EP2 Series can implement configuration of the Altera FPGA
over the IOS bus interface. The IOS-EP2 module uses the Altera passive
serial scheme with the IOS bus serving as the download path. Thus,
download and configuration are implemented with no special hardware or
cables.
CONFIGURATION
REGISTERS
CONFIGURATION
METHODOLOGIES
IOS-EP2 IOS Direct
Configuration Procedure