IOS-EP2 I/O SERVER MODULE Cyclone II Based FPGA Module
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corresponding input channel (i.e. any state transition, low to high or high to
low).
The Interrupt Type Configuration register at the carrier‟s base a
offset 0CH is used to control channels 00 through 07. For example, channel
00 is controlled via data bit-0 as seen in the table below.
Interrupt Type (COS or H/L) Configuration Register
MSB
LSB
Data
Bit 07
Data
Bit 06
Data
Bit 05
Data
Bit 04
Data
Bit 03
Data
Bit 02
Data
Bit 01
Data
Bit 00
Ch 07
Ch 06
Ch 05
Ch 04
Ch 03
Ch 02
Ch 01
Ch 00
Channel read or write operations use 8-bit, or 16-bit data transfers. The
upper 8 bits of this register are “Not Used” and will always read logic “0”.
Note that interrupts will not occur unless they are enabled via the Interrupt
Enable Register at base a offset 0AH.
All bits are set to “0” following a reset which means that, if enabled, the
inputs will cause interrupts for the levels specified by the digital input
channel Interrupt Polarity Register.
Interrupt Status Registers (Read/Write) - (Base + 0EH)
The Interrupt Status Register reflects the status of each of the
interrupting channels. A “1” bit indicates that an interrupt is pending for the
corresponding channel. A channel that does not have interrupts enabled
will never set its interrupt status flag. A channel‟s interrupt can be cleared
by writing a “1” to its bit position in the Interrupt Status Register (writing a “1”
acts as a reset signal to clear the set s
tate). This is known as the “Release
On Register Access” (RORA) method, as defined in the VME system
architecture specification. However, if the condition which caused the
interrupt to occur remains, the interrupt will be generated again (unless
disabled via the Interrupt Enable Register). In addition, an interrupt will be
generated if any of the channels enabled for interrupt have an interrupt
pending (i.e. one that has not been cleared). Writing “0” to a bit location has
no effect; that is, a pending interrupt will remain pending.
Note that interrupts are not prioritized via hardware. The system
software must handle interrupt prioritization.
The Interrupt Status register at the carrier‟s base a offset 0EH is
used to monitor pending interrupts corresponding to channels 00 through
07. For example, channel 00 is monitored via data bit-0.
The unused upper 8 bits of this register are “Not Used” and will always
read logic “0”. All bits are set to “0” following a reset, meaning that all
interrupts are cleared.
Interrupt Polarity Registers (Read/Write) - (Base + 10H)
The Interrupt Polarity Register determines the level that will cause a
channel interrupt to occur for each of the channels enabled for level
interrupts. A “0” bit specifies that an interrupt will occur when the
corresponding input channel is low (i.e. a “0” in the digital input channel data
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USER MODE