IOS-EP2 I/O SERVER MODULE Cyclone II Based FPGA Module
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Acromag, Inc. Tel:248-295-0310 Fax:248-624-9234 Email:[email protected] http://www.acromag.com
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Channel Configuration:
1 External LVTTL Clock input.
DC Electrical Characteristics:
V
IN
: 3.3V Maximum
V
IL
: 0.8V Maximum
V
IH
: 1.7V Minimum
Power-On Delay:
The IOS-EP2 has a power-up time of 0.3 seconds.
During this time the IOS module will not respond to any request. After this
initial power-on reset another 0.4 seconds maximum is required if loading
the FPGA from FLASH. During this time the board will act as if it is not
configured until the download to the FPGA is complete. It is good practice
to reset the board (using either an IOS bus or software reset) subsequent to
power-up.
EXTERNAL CLOCK INPUT
POWER-ON RESET