IOS-EP2 I/O SERVER MODULE Cyclone II Based FPGA Module
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1. Start the BitCalc2K1 Version 2 program, enter the desired
frequency, and select the IOS clock speed.
2. Hit the Calculate Button.
3. Write to the Clock Control Register 1 at base address
plus an offset of 18H using the data provided by the
program.
4. Write to the Clock Control Register 2 at base address
plus an offset of 1AH using the data provided by the
program.
5. Write to the Clock Control Register 3 at base address
plus an offset of 1CH using the data provided by the program.
6. Write 1H to the Clock Trigger Register at base address plus an offset
of 1EH.
After approximately 1.2ms, programming is complete and the clock is
available for use by the FPGA. A software or hardware reset during
programming will cause errors. If a reset occurs, repeat the above
procedure.
Programming Interrupts
Digital input channels can be programmed to generate interrupts for the
following conditions:
Change-of-State (COS) at selected input channels.
Input level (polarity) match at selected input channels.
Interrupts generated by the IOS-EP2 use interrupt request line
INTREQ0 (Interrupt Request 0). The interrupt release mechanism
employed is the Release On Register Access (RORA) type. This means
that the interrupter will release the I/O Server Module interrupt request line
(INTREQ0) after all pending interrupts have been cleared by writing a “1” to
the appropriate bit positions in the input channel Interrupt Status Register.
The Interrupt Vector Register contains a pointer vector to an interrupt
handling routine. One interrupt handling routine must be used to service all
possible channel interrupts.
When using interrupts, input channel bandwidth should be limited to
reduce the possibility of missing channel interrupts. For a given input
channel, this could happen if multiple changes occur before the channel‟s
interrupt is serviced. The response time of the input channels should also
be considered when calculating this bandwidth. The total response time is
the sum of the input buffer response time, plus the interrupt logic circuit
response time, and this time must pass before another interrupt condition
will be recognized. The Interrupt Input Response Time is specified in
section 6.